ARM: tegra: cardhu: Add 533MHz entry to EMC DFS table
Alex Frid [Thu, 10 Mar 2011 21:07:18 +0000 (13:07 -0800)]
Original-Change-Id: I8f80bbad3600e502d6ff71c51e6acaa41a5d4e1e
Reviewed-on: http://git-master/r/22659
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I223167759a875c912fb0af399c81757cd603e20d

Rebase-Id: R95c638f44042065e60c3a9c06b430b21cbb556ee

arch/arm/mach-tegra/board-cardhu-memory.c

index b438ad6..ba73e41 100644 (file)
@@ -489,6 +489,122 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g[] = {
                0x00200000,     /* DDR3 Mode Register 2 */
        },
        {
+               0x30,           /* Rev 2.0 */
+               533000,         /* SDRAM frquency */
+               {
+                       0x00000018,   /* EMC_RC */
+                       0x00000054,   /* EMC_RFC */
+                       0x00000011,   /* EMC_RAS */
+                       0x00000006,   /* EMC_RP */
+                       0x00000003,   /* EMC_R2W */
+                       0x00000009,   /* EMC_W2R */
+                       0x00000002,   /* EMC_R2P */
+                       0x0000000D,   /* EMC_W2P */
+                       0x00000006,   /* EMC_RD_RCD */
+                       0x00000006,   /* EMC_WR_RCD */
+                       0x00000002,   /* EMC_RRD */
+                       0x00000001,   /* EMC_REXT */
+                       0x00000000,   /* EMC_WEXT */
+                       0x00000005,   /* EMC_WDV */
+                       0x00000008,   /* EMC_QUSE */
+                       0x00000006,   /* EMC_QRST */
+                       0x0000000A,   /* EMC_QSAFE */
+                       0x00000010,   /* EMC_RDV */
+                       0x00000FFD,   /* EMC_REFRESH */
+                       0x00000000,   /* EMC_BURST_REFRESH_NUM */
+                       0x000003FF,   /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002,   /* EMC_PDEX2WR */
+                       0x00000002,   /* EMC_PDEX2RD */
+                       0x00000001,   /* EMC_PCHG2PDEN */
+                       0x00000000,   /* EMC_ACT2PDEN */
+                       0x0000000A,   /* EMC_AR2PDEN */
+                       0x00000012,   /* EMC_RW2PDEN */
+                       0x0000005B,   /* EMC_TXSR */
+                       0x00000200,   /* EMC_TXSRDLL */
+                       0x00000004,   /* EMC_TCKE */
+                       0x00000010,   /* EMC_TFAW */
+                       0x00000000,   /* EMC_TRPAB */
+                       0x00000005,   /* EMC_TCLKSTABLE */
+                       0x00000006,   /* EMC_TCLKSTOP */
+                       0x0000103E,   /* EMC_TREFBW */
+                       0x00000000,   /* EMC_QUSE_EXTRA */
+                       0x00000006,   /* EMC_FBIO_CFG6 */
+                       0x00000000,   /* EMC_ODT_WRITE */
+                       0x00000000,   /* EMC_ODT_READ */
+                       0x00007088,   /* EMC_FBIO_CFG5 */
+                       0xF0120441,   /* EMC_CFG_DIG_DLL */
+                       0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00010000,   /* EMC_DLL_XFORM_DQS0 */
+                       0x00010000,   /* EMC_DLL_XFORM_DQS1 */
+                       0x00010000,   /* EMC_DLL_XFORM_DQS2 */
+                       0x00010000,   /* EMC_DLL_XFORM_DQS3 */
+                       0x00010000,   /* EMC_DLL_XFORM_DQS4 */
+                       0x00010000,   /* EMC_DLL_XFORM_DQS5 */
+                       0x00010000,   /* EMC_DLL_XFORM_DQS6 */
+                       0x00010000,   /* EMC_DLL_XFORM_DQS7 */
+                       0x00008000,   /* EMC_DLL_XFORM_QUSE0 */
+                       0x00008000,   /* EMC_DLL_XFORM_QUSE1 */
+                       0x00008000,   /* EMC_DLL_XFORM_QUSE2 */
+                       0x00008000,   /* EMC_DLL_XFORM_QUSE3 */
+                       0x00008000,   /* EMC_DLL_XFORM_QUSE4 */
+                       0x00008000,   /* EMC_DLL_XFORM_QUSE5 */
+                       0x00008000,   /* EMC_DLL_XFORM_QUSE6 */
+                       0x00008000,   /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
+                       0x00020000,   /* EMC_DLL_XFORM_DQ0 */
+                       0x00020000,   /* EMC_DLL_XFORM_DQ1 */
+                       0x00020000,   /* EMC_DLL_XFORM_DQ2 */
+                       0x00020000,   /* EMC_DLL_XFORM_DQ3 */
+                       0x000202A0,   /* EMC_XM2CMDPADCTRL */
+                       0x0800013D,   /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000,   /* EMC_XM2DQPADCTRL2 */
+                       0x77FFD884,   /* EMC_XM2CLKPADCTRL */
+                       0x01F1F508,   /* EMC_XM2COMPPADCTRL */
+                       0x07077404,   /* EMC_XM2VTTGENPADCTRL */
+                       0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0800011D,   /* EMC_XM2QUSEPADCTRL */
+                       0x08000021,   /* EMC_XM2DQSPADCTRL3 */
+                       0x00000802,   /* EMC_CTT_TERM_CTRL */
+                       0x00020000,   /* EMC_ZCAL_INTERVAL */
+                       0x00000040,   /* EMC_ZCAL_WAIT_CNT */
+                       0x012B000C,   /* EMC_MRS_WAIT_CNT */
+                       0xA0F10000,   /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000,   /* EMC_CTT */
+                       0x00000000,   /* EMC_CTT_DURATION */
+                       0x800020AE,   /* EMC_DYN_SELF_REF_CONTROL */
+                       0x00000008,   /* MC_EMEM_ARB_CFG */
+                       0x80000060,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000002,   /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000003,   /* MC_EMEM_ARB_TIMING_RP */
+                       0x0000000D,   /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000008,   /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000007,   /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001,   /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000009,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002,   /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002,   /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003,   /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006,   /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030202,   /* MC_EMEM_ARB_DA_TURNS */
+                       0x0010090D,   /* MC_EMEM_ARB_DA_COVERS */
+                       0x7028180E,   /* MC_EMEM_ARB_MISC0 */
+                       0x001F0000,   /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x00000010,     /* EMC_AUTO_CAL_INTERVAL */
+               0x00001941,     /* DDR3 Mode Register 0 */
+               0x00100002,     /* DDR3 Mode Register 1 */
+               0x00200008,     /* DDR3 Mode Register 2 */
+       },
+       {
                0x30,           /* Rev 3.0 */
                667000,         /* SDRAM frquency */
                {