ARM: tegra: clock: Auto-detect PLLP rate in uart init
Alex Frid [Fri, 13 Jan 2012 01:39:04 +0000 (17:39 -0800)]
Tegra3 platform may boot with one of the predefined fixed PLLP
(peripheral PLL) output rates: 216MHz, 408MHz, or 204MHz. This
commit implements auto-detection of PLLP rate, and debug uart
configuration during kernel uart initialization.

Bug 928260

Change-Id: I3fac4c462f28ac3dc1c72c0cc0f8f87fa0a809c4
Reviewed-on: http://git-master/r/75849
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77294
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: R1decd75752d7578b6b2715211188921605cbf97d

arch/arm/mach-tegra/board-cardhu.c

index ba18c97..ce30afb 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/board-cardhu.c
  *
- * Copyright (c) 2011, NVIDIA Corporation.
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -377,6 +377,8 @@ static void __init uart_debug_init(void)
                        (board_info.board_id == BOARD_E1257))
                                debug_port_id = 1;
        }
+
+       tegra_init_debug_uart_rate();
        switch (debug_port_id) {
        case 0:
                /* UARTA is the debug port. */