Merge branch 'integration-2.6.39-for-tony' of git://git.pwsan.com/linux-integration...
Tony Lindgren [Fri, 11 Mar 2011 17:20:03 +0000 (09:20 -0800)]
Conflicts:
arch/arm/mach-omap2/pm34xx.c

1  2 
MAINTAINERS
arch/arm/mach-omap2/cpuidle34xx.c
arch/arm/mach-omap2/omap_twl.c
arch/arm/mach-omap2/opp3xxx_data.c
arch/arm/mach-omap2/opp4xxx_data.c
arch/arm/mach-omap2/pm.c
arch/arm/mach-omap2/pm24xx.c
arch/arm/mach-omap2/pm34xx.c
arch/arm/mach-omap2/smartreflex.c

diff --cc MAINTAINERS
Simple merge
Simple merge
Simple merge
  
  #include <plat/cpu.h>
  
+ #include "control.h"
  #include "omap_opp_data.h"
 +#include "pm.h"
  
+ /* 34xx */
+ /* VDD1 */
+ #define OMAP3430_VDD_MPU_OPP1_UV              975000
+ #define OMAP3430_VDD_MPU_OPP2_UV              1075000
+ #define OMAP3430_VDD_MPU_OPP3_UV              1200000
+ #define OMAP3430_VDD_MPU_OPP4_UV              1270000
+ #define OMAP3430_VDD_MPU_OPP5_UV              1350000
+ struct omap_volt_data omap34xx_vddmpu_volt_data[] = {
+       VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c),
+       VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c),
+       VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18),
+       VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18),
+       VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18),
+       VOLT_DATA_DEFINE(0, 0, 0, 0),
+ };
+ /* VDD2 */
+ #define OMAP3430_VDD_CORE_OPP1_UV             975000
+ #define OMAP3430_VDD_CORE_OPP2_UV             1050000
+ #define OMAP3430_VDD_CORE_OPP3_UV             1150000
+ struct omap_volt_data omap34xx_vddcore_volt_data[] = {
+       VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c),
+       VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c),
+       VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18),
+       VOLT_DATA_DEFINE(0, 0, 0, 0),
+ };
+ /* 36xx */
+ /* VDD1 */
+ #define OMAP3630_VDD_MPU_OPP50_UV             1012500
+ #define OMAP3630_VDD_MPU_OPP100_UV            1200000
+ #define OMAP3630_VDD_MPU_OPP120_UV            1325000
+ #define OMAP3630_VDD_MPU_OPP1G_UV             1375000
+ struct omap_volt_data omap36xx_vddmpu_volt_data[] = {
+       VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c),
+       VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16),
+       VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23),
+       VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27),
+       VOLT_DATA_DEFINE(0, 0, 0, 0),
+ };
+ /* VDD2 */
+ #define OMAP3630_VDD_CORE_OPP50_UV            1000000
+ #define OMAP3630_VDD_CORE_OPP100_UV           1200000
+ struct omap_volt_data omap36xx_vddcore_volt_data[] = {
+       VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c),
+       VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16),
+       VOLT_DATA_DEFINE(0, 0, 0, 0),
+ };
+ /* OPP data */
  static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
        /* MPU OPP1 */
        OPP_INITIALIZER("mpu", true, 125000000, 975000),
  
  #include <plat/cpu.h>
  
+ #include "control.h"
  #include "omap_opp_data.h"
 +#include "pm.h"
  
+ /*
+  * Structures containing OMAP4430 voltage supported and various
+  * voltage dependent data for each VDD.
+  */
+ #define OMAP4430_VDD_MPU_OPP50_UV             930000
+ #define OMAP4430_VDD_MPU_OPP100_UV            1100000
+ #define OMAP4430_VDD_MPU_OPPTURBO_UV          1260000
+ #define OMAP4430_VDD_MPU_OPPNITRO_UV          1350000
+ struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
+       VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
+       VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
+       VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
+       VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27),
+       VOLT_DATA_DEFINE(0, 0, 0, 0),
+ };
+ #define OMAP4430_VDD_IVA_OPP50_UV             930000
+ #define OMAP4430_VDD_IVA_OPP100_UV            1100000
+ #define OMAP4430_VDD_IVA_OPPTURBO_UV          1260000
+ struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
+       VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
+       VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16),
+       VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23),
+       VOLT_DATA_DEFINE(0, 0, 0, 0),
+ };
+ #define OMAP4430_VDD_CORE_OPP50_UV            930000
+ #define OMAP4430_VDD_CORE_OPP100_UV           1100000
+ struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
+       VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
+       VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16),
+       VOLT_DATA_DEFINE(0, 0, 0, 0),
+ };
  static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
        /* MPU OPP1 - OPP50 */
        OPP_INITIALIZER("mpu", true, 300000000, 1100000),
Simple merge
@@@ -363,11 -363,14 +363,11 @@@ static const struct platform_suspend_op
  /* XXX This function should be shareable between OMAP2xxx and OMAP3 */
  static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
  {
 -      clkdm_clear_all_wkdeps(clkdm);
 -      clkdm_clear_all_sleepdeps(clkdm);
 -
        if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
-               omap2_clkdm_allow_idle(clkdm);
+               clkdm_allow_idle(clkdm);
        else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
                 atomic_read(&clkdm->usecount) == 0)
-               omap2_clkdm_sleep(clkdm);
+               clkdm_sleep(clkdm);
        return 0;
  }
  
@@@ -406,9 -412,12 +409,9 @@@ static void __init prcm_setup_regs(void
  
        pwrdm = clkdm_get_pwrdm(gfx_clkdm);
        pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
-       omap2_clkdm_sleep(gfx_clkdm);
+       clkdm_sleep(gfx_clkdm);
  
 -      /*
 -       * Clear clockdomain wakeup dependencies and enable
 -       * hardware-supervised idle for all clkdms
 -       */
 +      /* Enable hardware-supervised idle for all clkdms */
        clkdm_for_each(clkdms_setup, NULL);
        clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
  
@@@ -690,107 -693,21 +688,7 @@@ static void __init prcm_setup_regs(void
        u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
                                        OMAP3630_GRPSEL_UART4_MASK : 0;
  
-       /*
-        * Enable interface clock autoidle for all modules.
-        * Note that in the long run this should be done by clockfw
-        */
-       omap2_cm_write_mod_reg(
-               OMAP3430_AUTO_MODEM_MASK |
-               OMAP3430ES2_AUTO_MMC3_MASK |
-               OMAP3430ES2_AUTO_ICR_MASK |
-               OMAP3430_AUTO_AES2_MASK |
-               OMAP3430_AUTO_SHA12_MASK |
-               OMAP3430_AUTO_DES2_MASK |
-               OMAP3430_AUTO_MMC2_MASK |
-               OMAP3430_AUTO_MMC1_MASK |
-               OMAP3430_AUTO_MSPRO_MASK |
-               OMAP3430_AUTO_HDQ_MASK |
-               OMAP3430_AUTO_MCSPI4_MASK |
-               OMAP3430_AUTO_MCSPI3_MASK |
-               OMAP3430_AUTO_MCSPI2_MASK |
-               OMAP3430_AUTO_MCSPI1_MASK |
-               OMAP3430_AUTO_I2C3_MASK |
-               OMAP3430_AUTO_I2C2_MASK |
-               OMAP3430_AUTO_I2C1_MASK |
-               OMAP3430_AUTO_UART2_MASK |
-               OMAP3430_AUTO_UART1_MASK |
-               OMAP3430_AUTO_GPT11_MASK |
-               OMAP3430_AUTO_GPT10_MASK |
-               OMAP3430_AUTO_MCBSP5_MASK |
-               OMAP3430_AUTO_MCBSP1_MASK |
-               OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
-               OMAP3430_AUTO_MAILBOXES_MASK |
-               OMAP3430_AUTO_OMAPCTRL_MASK |
-               OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
-               OMAP3430_AUTO_HSOTGUSB_MASK |
-               OMAP3430_AUTO_SAD2D_MASK |
-               OMAP3430_AUTO_SSI_MASK,
-               CORE_MOD, CM_AUTOIDLE1);
-       omap2_cm_write_mod_reg(
-               OMAP3430_AUTO_PKA_MASK |
-               OMAP3430_AUTO_AES1_MASK |
-               OMAP3430_AUTO_RNG_MASK |
-               OMAP3430_AUTO_SHA11_MASK |
-               OMAP3430_AUTO_DES1_MASK,
-               CORE_MOD, CM_AUTOIDLE2);
-       if (omap_rev() > OMAP3430_REV_ES1_0) {
-               omap2_cm_write_mod_reg(
-                       OMAP3430_AUTO_MAD2D_MASK |
-                       OMAP3430ES2_AUTO_USBTLL_MASK,
-                       CORE_MOD, CM_AUTOIDLE3);
-       }
-       omap2_cm_write_mod_reg(
-               OMAP3430_AUTO_WDT2_MASK |
-               OMAP3430_AUTO_WDT1_MASK |
-               OMAP3430_AUTO_GPIO1_MASK |
-               OMAP3430_AUTO_32KSYNC_MASK |
-               OMAP3430_AUTO_GPT12_MASK |
-               OMAP3430_AUTO_GPT1_MASK,
-               WKUP_MOD, CM_AUTOIDLE);
-       omap2_cm_write_mod_reg(
-               OMAP3430_AUTO_DSS_MASK,
-               OMAP3430_DSS_MOD,
-               CM_AUTOIDLE);
-       omap2_cm_write_mod_reg(
-               OMAP3430_AUTO_CAM_MASK,
-               OMAP3430_CAM_MOD,
-               CM_AUTOIDLE);
-       omap2_cm_write_mod_reg(
-               omap3630_auto_uart4_mask |
-               OMAP3430_AUTO_GPIO6_MASK |
-               OMAP3430_AUTO_GPIO5_MASK |
-               OMAP3430_AUTO_GPIO4_MASK |
-               OMAP3430_AUTO_GPIO3_MASK |
-               OMAP3430_AUTO_GPIO2_MASK |
-               OMAP3430_AUTO_WDT3_MASK |
-               OMAP3430_AUTO_UART3_MASK |
-               OMAP3430_AUTO_GPT9_MASK |
-               OMAP3430_AUTO_GPT8_MASK |
-               OMAP3430_AUTO_GPT7_MASK |
-               OMAP3430_AUTO_GPT6_MASK |
-               OMAP3430_AUTO_GPT5_MASK |
-               OMAP3430_AUTO_GPT4_MASK |
-               OMAP3430_AUTO_GPT3_MASK |
-               OMAP3430_AUTO_GPT2_MASK |
-               OMAP3430_AUTO_MCBSP4_MASK |
-               OMAP3430_AUTO_MCBSP3_MASK |
-               OMAP3430_AUTO_MCBSP2_MASK,
-               OMAP3430_PER_MOD,
-               CM_AUTOIDLE);
-       if (omap_rev() > OMAP3430_REV_ES1_0) {
-               omap2_cm_write_mod_reg(
-                       OMAP3430ES2_AUTO_USBHOST_MASK,
-                       OMAP3430ES2_USBHOST_MOD,
-                       CM_AUTOIDLE);
-       }
 -      /* XXX Reset all wkdeps. This should be done when initializing
 -       * powerdomains */
 -      omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
 -      omap2_prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
 -      omap2_prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
 -      omap2_prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
 -      omap2_prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
 -      omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
 -      if (omap_rev() > OMAP3430_REV_ES1_0) {
 -              omap2_prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
 -              omap2_prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 -      } else
 -              omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 -
+       /* XXX This should be handled by hwmod code or SCM init code */
        omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
  
        /*
Simple merge