ARM: tegra: power: Update Tegra3 EMC DFS table
Ray Poudrier [Wed, 22 Jun 2011 01:00:19 +0000 (18:00 -0700)]
Add EMC table for LP-DDR2 Samsung memory

Original-Change-Id: I931bbb0d2283ad94d130803cef7c08b6da5923a1
Reviewed-on: http://git-master/r/37757
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: Racdadadfeb4438faab94ca2bea4d9665da381d18

arch/arm/mach-tegra/board-cardhu-memory.c

index f839367..fab8400 100644 (file)
@@ -1084,6 +1084,594 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
        },
 };
 
+static const struct tegra_emc_table cardhu_emc_tables_k4p8g304eb[] = {
+       {
+               0x30,       /* Rev 3.0 */
+               25500,      /* SDRAM frequency */
+               {
+                       0x00000001, /* EMC_RC */
+                       0x00000003, /* EMC_RFC */
+                       0x00000002, /* EMC_RAS */
+                       0x00000002, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x00000004, /* EMC_W2R */
+                       0x00000001, /* EMC_R2P */
+                       0x00000005, /* EMC_W2P */
+                       0x00000002, /* EMC_RD_RCD */
+                       0x00000002, /* EMC_WR_RCD */
+                       0x00000001, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000001, /* EMC_WDV */
+                       0x00000003, /* EMC_QUSE */
+                       0x00000001, /* EMC_QRST */
+                       0x00000009, /* EMC_QSAFE */
+                       0x0000000a, /* EMC_RDV */
+                       0x0000005e, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000017, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000001, /* EMC_PDEX2WR */
+                       0x00000001, /* EMC_PDEX2RD */
+                       0x00000002, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000001, /* EMC_AR2PDEN */
+                       0x00000007, /* EMC_RW2PDEN */
+                       0x00000004, /* EMC_TXSR */
+                       0x00000004, /* EMC_TXSRDLL */
+                       0x00000003, /* EMC_TCKE */
+                       0x00000008, /* EMC_TFAW */
+                       0x00000004, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000002, /* EMC_TCLKSTOP */
+                       0x00000068, /* EMC_TREFBW */
+                       0x00000004, /* EMC_QUSE_EXTRA */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x00004282, /* EMC_FBIO_CFG5 */
+                       0x00780084, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00098000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00098000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00098000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00098000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00000010, /* EMC_DLL_XFORM_DQS4 */
+                       0x00000010, /* EMC_DLL_XFORM_DQS5 */
+                       0x00000010, /* EMC_DLL_XFORM_DQS6 */
+                       0x00000010, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000008, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000008, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000008, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000008, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00100220, /* EMC_XM2CMDPADCTRL */
+                       0x0800201c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc004, /* EMC_XM2CLKPADCTRL */
+                       0x01f1f008, /* EMC_XM2COMPPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x08000068, /* EMC_XM2QUSEPADCTRL */
+                       0x08000000, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00064000, /* EMC_ZCAL_INTERVAL */
+                       0x0000000a, /* EMC_ZCAL_WAIT_CNT */
+                       0x00090009, /* EMC_MRS_WAIT_CNT */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x800001c2, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x00020001, /* MC_EMEM_ARB_CFG */
+                       0x80000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x02020001, /* MC_EMEM_ARB_DA_TURNS */
+                       0x00060402, /* MC_EMEM_ARB_DA_COVERS */
+                       0x74030303, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000001, /* EMC_CFG.PERIODIC_QRST */
+               0x00000000, /* Mode Register 0 */
+               0x00010022, /* Mode Register 1 */
+               0x00020001, /* Mode Register 2 */
+       },
+       {
+               0x30,       /* Rev 3.0 */
+               51000,      /* SDRAM frequency */
+               {
+                       0x00000003, /* EMC_RC */
+                       0x00000006, /* EMC_RFC */
+                       0x00000002, /* EMC_RAS */
+                       0x00000002, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x00000004, /* EMC_W2R */
+                       0x00000001, /* EMC_R2P */
+                       0x00000005, /* EMC_W2P */
+                       0x00000002, /* EMC_RD_RCD */
+                       0x00000002, /* EMC_WR_RCD */
+                       0x00000001, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000001, /* EMC_WDV */
+                       0x00000003, /* EMC_QUSE */
+                       0x00000001, /* EMC_QRST */
+                       0x00000009, /* EMC_QSAFE */
+                       0x0000000a, /* EMC_RDV */
+                       0x000000c0, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000030, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000001, /* EMC_PDEX2WR */
+                       0x00000001, /* EMC_PDEX2RD */
+                       0x00000002, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000001, /* EMC_AR2PDEN */
+                       0x00000007, /* EMC_RW2PDEN */
+                       0x00000008, /* EMC_TXSR */
+                       0x00000008, /* EMC_TXSRDLL */
+                       0x00000003, /* EMC_TCKE */
+                       0x00000008, /* EMC_TFAW */
+                       0x00000004, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000002, /* EMC_TCLKSTOP */
+                       0x000000d5, /* EMC_TREFBW */
+                       0x00000004, /* EMC_QUSE_EXTRA */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x00004282, /* EMC_FBIO_CFG5 */
+                       0x00780084, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x000a0000, /* EMC_DLL_XFORM_DQS0 */
+                       0x000a0000, /* EMC_DLL_XFORM_DQS1 */
+                       0x000a0000, /* EMC_DLL_XFORM_DQS2 */
+                       0x000a0000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00000010, /* EMC_DLL_XFORM_DQS4 */
+                       0x00000010, /* EMC_DLL_XFORM_DQS5 */
+                       0x00000010, /* EMC_DLL_XFORM_DQS6 */
+                       0x00000010, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000018, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000018, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000018, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000018, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00100220, /* EMC_XM2CMDPADCTRL */
+                       0x0800201c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc004, /* EMC_XM2CLKPADCTRL */
+                       0x01f1f008, /* EMC_XM2COMPPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x08000068, /* EMC_XM2QUSEPADCTRL */
+                       0x08000000, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00064000, /* EMC_ZCAL_INTERVAL */
+                       0x00000013, /* EMC_ZCAL_WAIT_CNT */
+                       0x00090009, /* EMC_MRS_WAIT_CNT */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80000287, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x00010001, /* MC_EMEM_ARB_CFG */
+                       0x8000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x02020001, /* MC_EMEM_ARB_DA_TURNS */
+                       0x00060402, /* MC_EMEM_ARB_DA_COVERS */
+                       0x72c30303, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000001, /* EMC_CFG.PERIODIC_QRST */
+               0x00000000, /* Mode Register 0 */
+               0x00010022, /* Mode Register 1 */
+               0x00020001, /* Mode Register 2 */
+       },
+       {
+               0x30,       /* Rev 3.0 */
+               102000,     /* SDRAM frequency */
+               {
+                       0x00000006, /* EMC_RC */
+                       0x0000000d, /* EMC_RFC */
+                       0x00000004, /* EMC_RAS */
+                       0x00000002, /* EMC_RP */
+                       0x00000004, /* EMC_R2W */
+                       0x00000004, /* EMC_W2R */
+                       0x00000001, /* EMC_R2P */
+                       0x00000005, /* EMC_W2P */
+                       0x00000002, /* EMC_RD_RCD */
+                       0x00000002, /* EMC_WR_RCD */
+                       0x00000001, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000001, /* EMC_WDV */
+                       0x00000003, /* EMC_QUSE */
+                       0x00000001, /* EMC_QRST */
+                       0x00000009, /* EMC_QSAFE */
+                       0x00000009, /* EMC_RDV */
+                       0x00000181, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000001, /* EMC_PDEX2WR */
+                       0x00000001, /* EMC_PDEX2RD */
+                       0x00000002, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000001, /* EMC_AR2PDEN */
+                       0x00000007, /* EMC_RW2PDEN */
+                       0x0000000f, /* EMC_TXSR */
+                       0x0000000f, /* EMC_TXSRDLL */
+                       0x00000003, /* EMC_TCKE */
+                       0x00000008, /* EMC_TFAW */
+                       0x00000004, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000002, /* EMC_TCLKSTOP */
+                       0x000001a9, /* EMC_TREFBW */
+                       0x00000004, /* EMC_QUSE_EXTRA */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x00004282, /* EMC_FBIO_CFG5 */
+                       0x00780084, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x000a0000, /* EMC_DLL_XFORM_DQS0 */
+                       0x000a0000, /* EMC_DLL_XFORM_DQS1 */
+                       0x000a0000, /* EMC_DLL_XFORM_DQS2 */
+                       0x000a0000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00000010, /* EMC_DLL_XFORM_DQS4 */
+                       0x00000010, /* EMC_DLL_XFORM_DQS5 */
+                       0x00000010, /* EMC_DLL_XFORM_DQS6 */
+                       0x00000010, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000008, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000008, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000008, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000008, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00120220, /* EMC_XM2CMDPADCTRL */
+                       0x0800201c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc004, /* EMC_XM2CLKPADCTRL */
+                       0x01f1f008, /* EMC_XM2COMPPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x08000068, /* EMC_XM2QUSEPADCTRL */
+                       0x08000000, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00064000, /* EMC_ZCAL_INTERVAL */
+                       0x00000025, /* EMC_ZCAL_WAIT_CNT */
+                       0x00090009, /* EMC_MRS_WAIT_CNT */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x00000001, /* MC_EMEM_ARB_CFG */
+                       0x80000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x02020001, /* MC_EMEM_ARB_DA_TURNS */
+                       0x00060403, /* MC_EMEM_ARB_DA_COVERS */
+                       0x72430504, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               0x0000000a, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000001, /* EMC_CFG.PERIODIC_QRST */
+               0x00000000, /* Mode Register 0 */
+               0x00010022, /* Mode Register 1 */
+               0x00020001, /* Mode Register 2 */
+       },
+       {
+               0x30,       /* Rev 3.0 */
+               204000,     /* SDRAM frequency */
+               {
+                       0x0000000c, /* EMC_RC */
+                       0x0000001a, /* EMC_RFC */
+                       0x00000008, /* EMC_RAS */
+                       0x00000003, /* EMC_RP */
+                       0x00000005, /* EMC_R2W */
+                       0x00000004, /* EMC_W2R */
+                       0x00000001, /* EMC_R2P */
+                       0x00000006, /* EMC_W2P */
+                       0x00000003, /* EMC_RD_RCD */
+                       0x00000003, /* EMC_WR_RCD */
+                       0x00000002, /* EMC_RRD */
+                       0x00000002, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000001, /* EMC_WDV */
+                       0x00000003, /* EMC_QUSE */
+                       0x00000001, /* EMC_QRST */
+                       0x0000000a, /* EMC_QSAFE */
+                       0x0000000a, /* EMC_RDV */
+                       0x00000303, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000001, /* EMC_PDEX2WR */
+                       0x00000001, /* EMC_PDEX2RD */
+                       0x00000003, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000001, /* EMC_AR2PDEN */
+                       0x00000007, /* EMC_RW2PDEN */
+                       0x0000001d, /* EMC_TXSR */
+                       0x0000001d, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x0000000b, /* EMC_TFAW */
+                       0x00000005, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000002, /* EMC_TCLKSTOP */
+                       0x00000351, /* EMC_TREFBW */
+                       0x00000004, /* EMC_QUSE_EXTRA */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x00004282, /* EMC_FBIO_CFG5 */
+                       0x00440084, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00074000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00074000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00074000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00074000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00000010, /* EMC_DLL_XFORM_DQS4 */
+                       0x00000010, /* EMC_DLL_XFORM_DQS5 */
+                       0x00000010, /* EMC_DLL_XFORM_DQS6 */
+                       0x00000010, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000018, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000018, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000018, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000018, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x00078000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00078000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00078000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00100220, /* EMC_XM2CMDPADCTRL */
+                       0x0800201c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc004, /* EMC_XM2CLKPADCTRL */
+                       0x01f1f008, /* EMC_XM2COMPPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x08000068, /* EMC_XM2QUSEPADCTRL */
+                       0x08000000, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00064000, /* EMC_ZCAL_INTERVAL */
+                       0x0000004a, /* EMC_ZCAL_WAIT_CNT */
+                       0x00090009, /* EMC_MRS_WAIT_CNT */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x00000003, /* MC_EMEM_ARB_CFG */
+                       0x80000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x02030001, /* MC_EMEM_ARB_DA_TURNS */
+                       0x00070506, /* MC_EMEM_ARB_DA_COVERS */
+                       0x71e40a07, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000001, /* EMC_CFG.PERIODIC_QRST */
+               0x00000000, /* Mode Register 0 */
+               0x00010042, /* Mode Register 1 */
+               0x00020001, /* Mode Register 2 */
+       },
+       {
+               0x30,       /* Rev 3.0 */
+               533000,     /* SDRAM frequency */
+               {
+                       0x0000001f, /* EMC_RC */
+                       0x00000045, /* EMC_RFC */
+                       0x00000016, /* EMC_RAS */
+                       0x00000009, /* EMC_RP */
+                       0x00000008, /* EMC_R2W */
+                       0x00000009, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000d, /* EMC_W2P */
+                       0x00000009, /* EMC_RD_RCD */
+                       0x00000009, /* EMC_WR_RCD */
+                       0x00000005, /* EMC_RRD */
+                       0x00000003, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000004, /* EMC_WDV */
+                       0x0000000a, /* EMC_QUSE */
+                       0x00000006, /* EMC_QRST */
+                       0x0000000b, /* EMC_QSAFE */
+                       0x00000010, /* EMC_RDV */
+                       0x000007df, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x000001f7, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000003, /* EMC_PDEX2WR */
+                       0x00000003, /* EMC_PDEX2RD */
+                       0x00000009, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000001, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x0000004b, /* EMC_TXSR */
+                       0x0000004b, /* EMC_TXSRDLL */
+                       0x00000008, /* EMC_TCKE */
+                       0x0000001b, /* EMC_TFAW */
+                       0x0000000c, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000002, /* EMC_TCLKSTOP */
+                       0x000008aa, /* EMC_TREFBW */
+                       0x00000000, /* EMC_QUSE_EXTRA */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x00006282, /* EMC_FBIO_CFG5 */
+                       0x00120084, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00018000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00018000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00018000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00018000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00000010, /* EMC_DLL_XFORM_DQS4 */
+                       0x00000010, /* EMC_DLL_XFORM_DQS5 */
+                       0x00000010, /* EMC_DLL_XFORM_DQS6 */
+                       0x00000010, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000008, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000008, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000008, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000008, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x0002c000, /* EMC_DLL_XFORM_DQ0 */
+                       0x0002c000, /* EMC_DLL_XFORM_DQ1 */
+                       0x0002c000, /* EMC_DLL_XFORM_DQ2 */
+                       0x0002c000, /* EMC_DLL_XFORM_DQ3 */
+                       0x000b0220, /* EMC_XM2CMDPADCTRL */
+                       0x0800003d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc004, /* EMC_XM2CLKPADCTRL */
+                       0x01f1f408, /* EMC_XM2COMPPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x08000068, /* EMC_XM2QUSEPADCTRL */
+                       0x08000000, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00064000, /* EMC_ZCAL_INTERVAL */
+                       0x000000c0, /* EMC_ZCAL_WAIT_CNT */
+                       0x000e000e, /* EMC_MRS_WAIT_CNT */
+                       0xa0f10202, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x800010d9, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x00000008, /* MC_EMEM_ARB_CFG */
+                       0x80000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000010, /* MC_EMEM_ARB_TIMING_RC */
+                       0x0000000a, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x0000000d, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x05040002, /* MC_EMEM_ARB_DA_TURNS */
+                       0x00110b10, /* MC_EMEM_ARB_DA_COVERS */
+                       0x71c81811, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               0x00000030, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000001, /* EMC_CFG.PERIODIC_QRST */
+               0x00000000, /* Mode Register 0 */
+               0x000100c2, /* Mode Register 1 */
+               0x00020006, /* Mode Register 2 */
+       },
+};
+
 int cardhu_emc_init(void)
 {
        struct board_info board;
@@ -1091,7 +1679,9 @@ int cardhu_emc_init(void)
        tegra_get_board_info(&board);
 
        switch (board.board_id) {
-       case BOARD_PM269:       /* LPDDR2 table is not ready, yet */
+       case BOARD_PM269:
+               tegra_init_emc(cardhu_emc_tables_k4p8g304eb,
+                               ARRAY_SIZE(cardhu_emc_tables_k4p8g304eb));
                break;
        default:
                if (tegra_get_revision() == TEGRA_REVISION_A01)