ARM: tegra: t114: Mask UHS Modes for SDMMC1, SDMMC3
Naveen Kumar Arepalli [Mon, 28 Jan 2013 17:03:00 +0000 (22:03 +0530)]
Mask SDR104,DDR50,SDR50 modes for Dalmore(E1611)
Mask DDR 50 for ROTH.

Bug 1189241

Change-Id: I574315c2b557d9563a384db8f59c97bb0ddb5566
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/194740
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

arch/arm/mach-tegra/board-dalmore-sdhci.c
arch/arm/mach-tegra/board-pluto-sdhci.c
arch/arm/mach-tegra/board-roth-sdhci.c

index 6305842..be6031b 100644 (file)
@@ -33,6 +33,7 @@
 #include<mach/gpio-tegra.h>
 #include <mach/io_dpd.h>
 
+#include "tegra-board-id.h"
 #include "gpio-names.h"
 #include "board.h"
 #include "board-dalmore.h"
@@ -149,8 +150,6 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
        .trim_delay = 0x2,
        .ddr_clk_limit = 41000000,
        .max_clk_limit = 82000000,
-       .uhs_mask = MMC_UHS_MASK_SDR104 |
-               MMC_UHS_MASK_DDR50,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
@@ -387,6 +386,15 @@ subsys_initcall_sync(dalmore_wifi_prepower);
 
 int __init dalmore_sdhci_init(void)
 {
+       struct board_info board_info;
+
+       tegra_get_board_info(&board_info);
+       if (board_info.board_id == BOARD_E1611) {
+               tegra_sdhci_platform_data2.uhs_mask = MMC_UHS_MASK_SDR104 |
+                               MMC_UHS_MASK_DDR50 | MMC_UHS_MASK_SDR50;
+               tegra_sdhci_platform_data0.uhs_mask = MMC_UHS_MASK_SDR104 |
+                               MMC_UHS_MASK_DDR50 | MMC_UHS_MASK_SDR50;
+       }
        platform_device_register(&tegra_sdhci_device3);
        platform_device_register(&tegra_sdhci_device2);
        platform_device_register(&tegra_sdhci_device0);
index f05679d..7eed93e 100644 (file)
@@ -146,8 +146,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
        .trim_delay = 0x2,
        .ddr_clk_limit = 41000000,
        .max_clk_limit = 82000000,
-       .uhs_mask = MMC_UHS_MASK_SDR104 |
-               MMC_UHS_MASK_DDR50,
+       .uhs_mask = MMC_UHS_MASK_DDR50,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
@@ -158,6 +157,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
        .trim_delay = 0x3,
        .ddr_clk_limit = 41000000,
        .max_clk_limit = 82000000,
+       .uhs_mask = MMC_UHS_MASK_DDR50,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
index e1088bc..357a3fe 100644 (file)
@@ -150,8 +150,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
        .trim_delay = 0x2,
        .ddr_clk_limit = 41000000,
        .max_clk_limit = 82000000,
-       .uhs_mask = MMC_UHS_MASK_SDR104 |
-               MMC_UHS_MASK_DDR50,
+       .uhs_mask = MMC_UHS_MASK_DDR50,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
@@ -162,8 +161,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
        .trim_delay = 0x3,
        .ddr_clk_limit = 41000000,
        .max_clk_limit = 82000000,
-       .uhs_mask = MMC_UHS_MASK_SDR104 |
-                       MMC_UHS_MASK_DDR50,
+       .uhs_mask = MMC_UHS_MASK_DDR50,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {