MIPS: Remove execution hazard barriers for Octeon.
David Daney [Tue, 12 May 2009 19:41:54 +0000 (12:41 -0700)]
The Octeon has no execution hazards, so we can remove them and save an
instruction per TLB handler invocation.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Reviewed by: David VomLehn <dvomlehn@cisco.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h

index 04ce6e6..bb291f4 100644 (file)
@@ -47,6 +47,7 @@
 #define cpu_has_mips32r2       0
 #define cpu_has_mips64r1       0
 #define cpu_has_mips64r2       1
+#define cpu_has_mips_r2_exec_hazard 0
 #define cpu_has_dsp            0
 #define cpu_has_mipsmt         0
 #define cpu_has_userlocal      0