ARM: tegra11: clock: Enable PLLE VREG
Alex Frid [Wed, 10 Oct 2012 02:00:28 +0000 (19:00 -0700)]
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/142829
(cherry picked from commit 099ccea9a52f351826a1200759e67718213ac1a1)

Change-Id: I95aa4bc199633693810fda505156444137da120e
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146274
Reviewed-by: Automatic_Commit_Validation_User

arch/arm/mach-tegra/tegra11_clocks.c

index e880555..9cf875b 100644 (file)
 #define PLLE_MISC_IDDQ_SW_VALUE                (1<<13)
 #define PLLE_MISC_LOCK                 (1<<11)
 #define PLLE_MISC_LOCK_ENABLE          (1<<9)
+#define PLLE_MISC_PLLE_PTS             (1<<8)
+#define PLLE_MISC_VREG_BG_CTRL_SHIFT   4
+#define PLLE_MISC_VREG_BG_CTRL_MASK    (0x3<<PLLE_MISC_VREG_BG_CTRL_SHIFT)
+#define PLLE_MISC_VREG_CTRL_SHIFT      2
+#define PLLE_MISC_VREG_CTRL_MASK       (0x3<<PLLE_MISC_VREG_CTRL_SHIFT)
 
 #define PLLE_SS_CTRL                   0x68
 #define        PLLE_SS_CNTL_SSC_BYP            (0x1 << 12)
@@ -3113,7 +3118,7 @@ static int tegra11_plle_clk_enable(struct clk *c)
        }
 
        /* setup locking configuration, s/w control of IDDQ and enable modes,
-          take pll out of IDDQ via s/w control */
+          take pll out of IDDQ via s/w control, setup VREG */
        val = clk_readl(c->reg + PLL_BASE);
        val &= ~PLLE_BASE_LOCK_OVERRIDE;
        clk_writel(val, c->reg + PLL_BASE);
@@ -3127,6 +3132,8 @@ static int tegra11_plle_clk_enable(struct clk *c)
        val |= PLLE_MISC_LOCK_ENABLE;
        val |= PLLE_MISC_IDDQ_SW_CTRL;
        val &= ~PLLE_MISC_IDDQ_SW_VALUE;
+       val |= PLLE_MISC_PLLE_PTS;
+       val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;
        clk_writel(val, c->reg + PLL_MISC(c));
        udelay(5);