arm: tegra: xmm: simultaneous L3 to L0 wakeup
Vinayak Pane [Fri, 27 Apr 2012 22:01:05 +0000 (15:01 -0700)]
In AP initiated L3->L0 wakeup xmm power state is set BBXMM_PS_L3TOL0
but if CP is also trying to wakeup then ipc_ap_wake_irq with falling
edge treats it incorrectly as CP wakeup pending - new race condition.

Adding a check to fix this scenario for both L3 and L3TOL0 states.

Bug 966077

Change-Id: I3af3538b48745588f17e4c13a3e23e4033f21821
Signed-off-by: Vinayak Pane <vpane@nvidia.com>
Reviewed-on: http://git-master/r/102698
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Steve Lin <stlin@nvidia.com>

arch/arm/mach-tegra/baseband-xmm-power.c

index 32d46d4..75ad8d2 100644 (file)
@@ -516,7 +516,8 @@ irqreturn_t xmm_power_ipc_ap_wake_irq(int irq, void *dev_id)
                        pr_info("Set wakeup_pending = 1 in system_"
                                        " suspending!!!\n");
                } else {
-                       if (baseband_xmm_powerstate == BBXMM_PS_L3) {
+                       if ((baseband_xmm_powerstate == BBXMM_PS_L3) ||
+                               (baseband_xmm_powerstate == BBXMM_PS_L3TOL0)) {
                                spin_unlock(&xmm_lock);
                                pr_info(" CP L3 -> L0\n");
                        } else if (baseband_xmm_powerstate == BBXMM_PS_L2) {