ARM: Tegra: P1852: changed nor timing regs and freq
Mohit Kataria [Fri, 18 May 2012 12:11:29 +0000 (17:11 +0530)]
Nor frequency and timing registers changed as per
values provided by syseng

Bug 978870

Change-Id: I18313c7df6265ddd4140d264ac2751ed8f1982df
Reviewed-on: http://git-master/r/103355
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Mohit Kataria <mkataria@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

arch/arm/mach-tegra/board-p1852.c

index ce0ff32..4851bca 100644 (file)
@@ -103,7 +103,7 @@ static __initdata struct tegra_clk_init_table p1852_clk_init_table[] = {
        { "pll_a",              NULL,           552960000,      false},
        { "pll_a_out0",         NULL,           12288000,       false},
        { "d_audio",            "pll_a_out0",   12288000,       false},
-       { "nor",                "pll_p",        86500000,       true},
+       { "nor",                "pll_p",        102000000,      true},
        { "uarta",              "pll_p",        480000000,      true},
        { "uartd",              "pll_p",        480000000,      true},
        { "uarte",              "pll_p",        480000000,      true},
@@ -409,12 +409,12 @@ static struct tegra_nor_platform_data p1852_nor_data = {
        .chip_parms = {
                /* FIXME: Need to use characterized value */
                .timing_default = {
-                       .timing0 = 0xA0400273,
-                       .timing1 = 0x00030402,
+                       .timing0 = 0x30300263,
+                       .timing1 = 0x00030302,
                },
                .timing_read = {
-                       .timing0 = 0xA0400273,
-                       .timing1 = 0x00030402,
+                       .timing0 = 0x30300263,
+                       .timing1 = 0x00030302,
                },
        },
 };