ARM: tegra: cardhu: Specify PLLD2 as backup clock source
Alex Frid [Sun, 15 Jan 2012 06:54:23 +0000 (22:54 -0800)]
Since not all possible PLLP output rates (216MHz, 408MHz or 204MHz)
can provide accurate enough pixel clock rate for cardhu panel, use
PLLD2 as backup clock source.

Bug 928260

Change-Id: I767e621606e849cb7d1976fbed198b9427660544
Reviewed-on: http://git-master/r/76034
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76816
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Rebase-Id: R226265d2fb62d8562ac89b11e0635aa8017c1e71

arch/arm/mach-tegra/board-cardhu-panel.c

index 155b614..3929c49 100644 (file)
@@ -938,6 +938,8 @@ static struct tegra_dc_out cardhu_disp1_out = {
        .parent_clk     = "pll_p",
 
 #ifndef CONFIG_TEGRA_CARDHU_DSI
+       .parent_clk_backup = "pll_d2_out0",
+
        .type           = TEGRA_DC_OUT_RGB,
        .depth          = 18,
        .dither         = TEGRA_DC_ORDERED_DITHER,