drm/radeon/kms: setup mc chremap properly on r7xx/evergreen
Alex Deucher [Mon, 22 Nov 2010 22:56:18 +0000 (17:56 -0500)]
Should improve performance slightly and possibly fix some
issues.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

drivers/gpu/drm/radeon/evergreen.c
drivers/gpu/drm/radeon/evergreend.h
drivers/gpu/drm/radeon/rv770.c
drivers/gpu/drm/radeon/rv770d.h

index 4dc5b47..728358e 100644 (file)
@@ -1382,6 +1382,42 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
        return backend_map;
 }
 
+static void evergreen_program_channel_remap(struct radeon_device *rdev)
+{
+       u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
+
+       tmp = RREG32(MC_SHARED_CHMAP);
+       switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
+       case 0:
+       case 1:
+       case 2:
+       case 3:
+       default:
+               /* default mapping */
+               mc_shared_chremap = 0x00fac688;
+               break;
+       }
+
+       switch (rdev->family) {
+       case CHIP_HEMLOCK:
+       case CHIP_CYPRESS:
+               tcp_chan_steer_lo = 0x54763210;
+               tcp_chan_steer_hi = 0x0000ba98;
+               break;
+       case CHIP_JUNIPER:
+       case CHIP_REDWOOD:
+       case CHIP_CEDAR:
+       default:
+               tcp_chan_steer_lo = 0x76543210;
+               tcp_chan_steer_hi = 0x0000ba98;
+               break;
+       }
+
+       WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
+       WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
+       WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
+}
+
 static void evergreen_gpu_init(struct radeon_device *rdev)
 {
        u32 cc_rb_backend_disable = 0;
@@ -1685,6 +1721,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
        WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
        WREG32(HDP_ADDR_CONFIG, gb_addr_config);
 
+       evergreen_program_channel_remap(rdev);
+
        num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
        grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
 
index 113c70c..9644b1c 100644 (file)
 #define MC_SHARED_CHMAP                                                0x2004
 #define                NOOFCHAN_SHIFT                                  12
 #define                NOOFCHAN_MASK                                   0x00003000
+#define MC_SHARED_CHREMAP                                      0x2008
 
 #define        MC_ARB_RAMCFG                                   0x2760
 #define                NOOFBANK_SHIFT                                  0
 #define                SYNC_WALKER                                     (1 << 25)
 #define                SYNC_ALIGNER                                    (1 << 26)
 
+#define        TCP_CHAN_STEER_LO                               0x960c
+#define        TCP_CHAN_STEER_HI                               0x9610
+
 #define        VGT_CACHE_INVALIDATION                          0x88C4
 #define                CACHE_INVALIDATION(x)                           ((x) << 0)
 #define                        VC_ONLY                                         0
index 4dfead8..24ebd08 100644 (file)
@@ -489,6 +489,49 @@ static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
        return backend_map;
 }
 
+static void rv770_program_channel_remap(struct radeon_device *rdev)
+{
+       u32 tcp_chan_steer, mc_shared_chremap, tmp;
+       bool force_no_swizzle;
+
+       switch (rdev->family) {
+       case CHIP_RV770:
+       case CHIP_RV730:
+               force_no_swizzle = false;
+               break;
+       case CHIP_RV710:
+       case CHIP_RV740:
+       default:
+               force_no_swizzle = true;
+               break;
+       }
+
+       tmp = RREG32(MC_SHARED_CHMAP);
+       switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
+       case 0:
+       case 1:
+       default:
+               /* default mapping */
+               mc_shared_chremap = 0x00fac688;
+               break;
+       case 2:
+       case 3:
+               if (force_no_swizzle)
+                       mc_shared_chremap = 0x00fac688;
+               else
+                       mc_shared_chremap = 0x00bbc298;
+               break;
+       }
+
+       if (rdev->family == CHIP_RV740)
+               tcp_chan_steer = 0x00ef2a60;
+       else
+               tcp_chan_steer = 0x00fac688;
+
+       WREG32(TCP_CHAN_STEER, tcp_chan_steer);
+       WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
+}
+
 static void rv770_gpu_init(struct radeon_device *rdev)
 {
        int i, j, num_qd_pipes;
@@ -688,6 +731,8 @@ static void rv770_gpu_init(struct radeon_device *rdev)
        WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
        WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 
+       rv770_program_channel_remap(rdev);
+
        WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
        WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
        WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
index b7a5a20..7b1c8f8 100644 (file)
 #define MC_SHARED_CHMAP                                                0x2004
 #define                NOOFCHAN_SHIFT                                  12
 #define                NOOFCHAN_MASK                                   0x00003000
+#define MC_SHARED_CHREMAP                                      0x2008
 
 #define        MC_ARB_RAMCFG                                   0x2760
 #define                NOOFBANK_SHIFT                                  0
 #define                BILINEAR_PRECISION_8_BIT                        (1 << 31)
 
 #define        TCP_CNTL                                        0x9610
+#define        TCP_CHAN_STEER                                  0x9614
 
 #define        VGT_CACHE_INVALIDATION                          0x88C4
 #define                CACHE_INVALIDATION(x)                           ((x)<<0)