Add support for SB1A CPU.
Andrew Isaacson [Thu, 20 Oct 2005 06:56:20 +0000 (23:56 -0700)]
Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

arch/mips/kernel/cpu-probe.c
arch/mips/kernel/proc.c
arch/mips/mm/tlbex.c
include/asm-mips/addrspace.h
include/asm-mips/cpu.h

index f7a8415..a263fb7 100644 (file)
@@ -623,6 +623,9 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
                c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 #endif
                break;
+       case PRID_IMP_SB1A:
+               c->cputype = CPU_SB1A;
+               break;
        }
 }
 
index f2b0446..86fe15b 100644 (file)
@@ -56,6 +56,7 @@ static const char *cpu_name[] = {
         [CPU_5KC]      = "MIPS 5Kc",
        [CPU_R4310]     = "R4310",
        [CPU_SB1]       = "SiByte SB1",
+       [CPU_SB1A]      = "SiByte SB1A",
        [CPU_TX3912]    = "TX3912",
        [CPU_TX3922]    = "TX3922",
        [CPU_TX3927]    = "TX3927",
index 240537d..0f94858 100644 (file)
@@ -854,6 +854,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
        case CPU_R12000:
        case CPU_4KC:
        case CPU_SB1:
+       case CPU_SB1A:
        case CPU_4KSC:
        case CPU_20KC:
        case CPU_25KF:
index 16c1c08..42520cc 100644 (file)
 #define TO_PHYS_MASK   _LLCONST_(0x000000ffffffffff)   /* 2^^40 - 1 */
 #endif
 
-#if defined(CONFIG_CPU_SB1)
+#if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A)
 #define KUSIZE         _LLCONST_(0x0000100000000000)   /* 2^^44 */
 #define KUSIZE_64      _LLCONST_(0x0000100000000000)   /* 2^^44 */
 #define K0SIZE         _LLCONST_(0x0000100000000000)   /* 2^^44 */
index 46b2a8d..48eac29 100644 (file)
@@ -93,6 +93,7 @@
  */
 
 #define PRID_IMP_SB1            0x0100
+#define PRID_IMP_SB1A           0x1100
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
 #define CPU_AU1200             59
 #define CPU_34K                        60
 #define CPU_PR4450             61
-#define CPU_LAST               61
+#define CPU_SB1A               62
+#define CPU_LAST               62
 
 /*
  * ISA Level encodings