drm/i915: Enable/disable the dithering for LVDS based on VBT setting
Zhao Yakui [Mon, 4 Jan 2010 08:29:30 +0000 (16:29 +0800)]
Enable/disable the dithering for LVDS based on VBT setting. On the 965/g4x
platform the dithering flag is defined in LVDS register. And on the ironlake
the dithering flag is defined in pipeconf register.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>

drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_display.c

index f79b133..149d360 100644 (file)
 #define   LVDS_PORT_EN                 (1 << 31)
 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
 #define   LVDS_PIPEB_SELECT            (1 << 30)
+/* LVDS dithering flag on 965/g4x platform */
+#define   LVDS_ENABLE_DITHER           (1 << 25)
 /* Enable border for unscaled (or aspect-scaled) display */
 #define   LVDS_BORDER_ENABLE           (1 << 15)
 /*
 
 /* Display & cursor control */
 
+/* dithering flag on Ironlake */
+#define PIPE_ENABLE_DITHER     (1 << 4)
 /* Pipe A */
 #define PIPEADSL               0x70000
 #define PIPEACONF              0x70008
index 84705b7..0c9b79f 100644 (file)
@@ -3195,7 +3195,20 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                 * appropriately here, but we need to look more thoroughly into how
                 * panels behave in the two modes.
                 */
-
+               /* set the dithering flag */
+               if (IS_I965G(dev)) {
+                       if (dev_priv->lvds_dither) {
+                               if (IS_IRONLAKE(dev))
+                                       pipeconf |= PIPE_ENABLE_DITHER;
+                               else
+                                       lvds |= LVDS_ENABLE_DITHER;
+                       } else {
+                               if (IS_IRONLAKE(dev))
+                                       pipeconf &= ~PIPE_ENABLE_DITHER;
+                               else
+                                       lvds &= ~LVDS_ENABLE_DITHER;
+                       }
+               }
                I915_WRITE(lvds_reg, lvds);
                I915_READ(lvds_reg);
        }