ARM: tegra: wdt: Add support for Tegra3 CPU WDTs
Kamal Kannan Balagopalan [Tue, 12 Jun 2012 21:38:43 +0000 (14:38 -0700)]
Tegra3 adds new CPU watchdog timers. Add device support for the
CPU WDTs.

Bug 857748

Change-Id: I0f99c37fed89879d39667b734654c659fe631aaf
Signed-off-by: Kamal Kannan Balagopalan <kbalagopalan@nvidia.com>
Reviewed-on: http://git-master/r/108379
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

arch/arm/mach-tegra/devices.c
arch/arm/mach-tegra/devices.h
arch/arm/mach-tegra/wdt-recovery.c

index 32fb597..25a4d71 100644 (file)
@@ -1727,6 +1727,79 @@ static struct resource tegra_wdt_resources[] = {
                .flags  = IORESOURCE_IRQ,
        },
 };
+
+static struct resource tegra_wdt0_resources[] = {
+       [0] = {
+               .start  = TEGRA_WDT0_BASE,
+               .end    = TEGRA_WDT0_BASE + TEGRA_WDT0_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = TEGRA_TMR7_BASE,
+               .end    = TEGRA_TMR7_BASE + TEGRA_TMR7_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [2] = {
+               .start  = INT_WDT_CPU,
+               .end    = INT_WDT_CPU,
+               .flags  = IORESOURCE_IRQ,
+       },
+#ifdef CONFIG_TEGRA_FIQ_DEBUGGER
+       [3] = {
+               .start  = TEGRA_QUATERNARY_ICTLR_BASE,
+               .end    = TEGRA_QUATERNARY_ICTLR_BASE + \
+                               TEGRA_QUATERNARY_ICTLR_SIZE -1,
+               .flags  = IORESOURCE_MEM,
+       },
+#endif
+};
+
+static struct resource tegra_wdt1_resources[] = {
+       [0] = {
+               .start  = TEGRA_WDT1_BASE,
+               .end    = TEGRA_WDT1_BASE + TEGRA_WDT1_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = TEGRA_TMR8_BASE,
+               .end    = TEGRA_TMR8_BASE + TEGRA_TMR8_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct resource tegra_wdt2_resources[] = {
+       [0] = {
+               .start  = TEGRA_WDT2_BASE,
+               .end    = TEGRA_WDT2_BASE + TEGRA_WDT2_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start  = TEGRA_TMR9_BASE,
+               .end    = TEGRA_TMR9_BASE + TEGRA_TMR9_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+struct platform_device tegra_wdt0_device = {
+       .name           = "tegra_wdt",
+       .id             = 0,
+       .num_resources  = ARRAY_SIZE(tegra_wdt0_resources),
+       .resource       = tegra_wdt0_resources,
+};
+
+struct platform_device tegra_wdt1_device = {
+       .name           = "tegra_wdt",
+       .id             = 1,
+       .num_resources  = ARRAY_SIZE(tegra_wdt1_resources),
+       .resource       = tegra_wdt1_resources,
+};
+
+struct platform_device tegra_wdt2_device = {
+       .name           = "tegra_wdt",
+       .id             = 2,
+       .num_resources  = ARRAY_SIZE(tegra_wdt2_resources),
+       .resource       = tegra_wdt2_resources,
+};
 #endif
 
 struct platform_device tegra_wdt_device = {
index 9a0c1f4..fd06f23 100644 (file)
@@ -128,6 +128,11 @@ extern struct platform_device tegra_gart_device;
 extern struct platform_device tegra_smmu_device;
 #endif
 extern struct platform_device tegra_wdt_device;
+#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
+extern struct platform_device tegra_wdt0_device;
+extern struct platform_device tegra_wdt1_device;
+extern struct platform_device tegra_wdt2_device;
+#endif
 extern struct platform_device tegra_pwfm0_device;
 extern struct platform_device tegra_pwfm1_device;
 extern struct platform_device tegra_pwfm2_device;
index f5a18bb..c0a1a1f 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/wdt-recovery.c
  *
- * Copyright (c) 2011, NVIDIA Corporation.
+ * Copyright (c) 2012, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -45,7 +45,7 @@ static int wdt_heartbeat = 30;
 #define TIMER_PCR                      0x4
  #define TIMER_PCR_INTR                        (1 << 30)
 #define WDT_CFG                                (0)
- #define WDT_CFG_TMR_SRC               (7 << 0) /* for TMR7. */
+ #define WDT_CFG_TMR_SRC               (0 << 0) /* for TMR10. */
  #define WDT_CFG_PERIOD                        (1 << 4)
  #define WDT_CFG_INT_EN                        (1 << 12)
  #define WDT_CFG_SYS_RST_EN            (1 << 14)
@@ -56,8 +56,8 @@ static int wdt_heartbeat = 30;
 #define WDT_UNLOCK                     (0xC)
  #define WDT_UNLOCK_PATTERN            (0xC45A << 0)
 
-static void __iomem *wdt_timer  = IO_ADDRESS(TEGRA_TMR7_BASE);
-static void __iomem *wdt_source = IO_ADDRESS(TEGRA_WDT0_BASE);
+static void __iomem *wdt_timer  = IO_ADDRESS(TEGRA_TMR10_BASE);
+static void __iomem *wdt_source = IO_ADDRESS(TEGRA_WDT3_BASE);
 
 static void tegra_wdt_reset_enable(void)
 {