arm: tegra: la: Add config option for latency allowance.
Krishna Reddy [Thu, 23 Aug 2012 20:57:47 +0000 (13:57 -0700)]
This allows enable/disable latency allowance.

Change-Id: Iee2cb320f40de902e0c2792c516d7ac108451224
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/126984
GVS: Gerrit_Virtual_Submit

arch/arm/mach-tegra/Kconfig
arch/arm/mach-tegra/Makefile
arch/arm/mach-tegra/include/mach/latency_allowance.h

index 2897d07..baa0739 100644 (file)
@@ -85,6 +85,7 @@ config ARCH_TEGRA_3x_SOC
        select CPA
        select NVMAP_CACHE_MAINT_BY_SET_WAYS
        select PL310_ERRATA_727915
+       select TEGRA_LATENCY_ALLOWANCE if !TEGRA_FPGA_PLATFORM
        help
          Support for NVIDIA Tegra T30 processor family, based on the
          ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
@@ -687,6 +688,15 @@ config TEGRA_LP1_950
        depends on ARCH_TEGRA_3x_SOC
        help
                Enable support for LP1 Core voltage to set to lowest
+config TEGRA_LATENCY_ALLOWANCE
+       bool "Allow memory clients to configure latency allowance"
+       help
+         Latency allowance is a per-memory-client setting that tells the
+         memory controller how long it can ignore a request in favor of
+         others. In other words, It indicates how long a request from specific
+         memory client can wait before it is served.
+         Enabling this option allows memory clients configure the
+         latency allowance as per their bandwidth requirement.
 endif
 
 config TEGRA_DC_USE_HW_BPP
index 17b4843..ede91dd 100644 (file)
@@ -72,7 +72,7 @@ obj-$(CONFIG_ARCH_TEGRA_11x_SOC)        += tegra11_dvfs.o
 ifeq ($(CONFIG_TEGRA_SILICON_PLATFORM),y)
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_dvfs.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra3_dvfs.o
-obj-y                                   += latency_allowance.o
+obj-$(CONFIG_TEGRA_LATENCY_ALLOWANCE)   += latency_allowance.o
 obj-$(CONFIG_TEGRA_EDP_LIMITS)          += edp.o
 endif
 ifeq ($(CONFIG_TEGRA_SILICON_PLATFORM),y)
index 3f4764b..aaab168 100644 (file)
@@ -88,7 +88,7 @@ enum tegra_la_id {
        TEGRA_LA_MAX_ID
 };
 
-#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || !defined(CONFIG_TEGRA_SILICON_PLATFORM)
+#if !defined(CONFIG_TEGRA_LATENCY_ALLOWANCE)
 static inline int tegra_set_latency_allowance(enum tegra_la_id id,
                                                unsigned int bandwidth_in_mbps)
 {