video: tegra: dc: fix pixel clock latency issue
Ken Chang [Mon, 13 Feb 2012 03:22:21 +0000 (11:22 +0800)]
GENERAL_ACT_REQ causes double-buffered registers to become active.
This register needs to be programed to reduce the latency of pixel clock after
dc enabled by tegra_dc_enable().

bug 926189

Signed-off-by: Ken Chang <kenc@nvidia.com>
Reviewed-on: http://git-master/r/83346
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
(cherry picked from commit f39c5ddd1867c508900c9aa2d4eead7eb3082343)

Change-Id: I741c9be9074709c1ab571aa631cb462599d5fb78
Reviewed-on: http://git-master/r/84561
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

drivers/video/tegra/dc/dc.c

index 2ee5860..ab77b7e 100644 (file)
@@ -1706,6 +1706,9 @@ static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode
                         (mode->h_active << 16) | mode->v_active);
 #endif
 
+       tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
+       tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
+
        return 0;
 }