mmc: sdhci: Use quirks2 for defining new quirks
Pavan Kunapuli [Tue, 6 Aug 2013 10:10:26 +0000 (15:10 +0530)]
Revert back quirks to 32 bits long and use quirks2 to define any new
required quirks.

Bug 1330567

Change-Id: I5e7095fb18b2ccd19df44338e42b2a69d94be787
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/260564
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
GVS: Gerrit_Virtual_Submit

drivers/mmc/host/sdhci-pltfm.h
drivers/mmc/host/sdhci-tegra.c
drivers/mmc/host/sdhci.c
include/linux/mmc/sdhci.h

index d2809f7..e5b0c29 100644 (file)
@@ -17,7 +17,7 @@
 
 struct sdhci_pltfm_data {
        struct sdhci_ops *ops;
-       u64 quirks;
+       u32 quirks;
        u32 quirks2;
 };
 
index 623a205..f0c28f2 100644 (file)
@@ -2377,8 +2377,6 @@ static struct sdhci_pltfm_data sdhci_tegra20_pdata = {
        .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
                  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
-                 SDHCI_QUIRK_NON_STD_VOLTAGE_SWITCHING |
-                 SDHCI_QUIRK_NON_STANDARD_TUNING |
 #endif
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
                  SDHCI_QUIRK_NONSTANDARD_CLOCK |
@@ -2386,9 +2384,11 @@ static struct sdhci_pltfm_data sdhci_tegra20_pdata = {
                  SDHCI_QUIRK_SINGLE_POWER_WRITE |
                  SDHCI_QUIRK_NO_HISPD_BIT |
                  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
-                 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
-                 SDHCI_QUIRK_NO_CALC_MAX_DISCARD_TO,
-       .quirks2 = SDHCI_QUIRK2_BROKEN_PRESET_VALUES,
+                 SDHCI_QUIRK_BROKEN_CARD_DETECTION,
+       .quirks2 = SDHCI_QUIRK2_BROKEN_PRESET_VALUES |
+                 SDHCI_QUIRK2_NON_STD_VOLTAGE_SWITCHING |
+                 SDHCI_QUIRK2_NON_STANDARD_TUNING |
+                 SDHCI_QUIRK2_NO_CALC_MAX_DISCARD_TO,
        .ops  = &tegra_sdhci_ops,
 };
 
index 5ff3755..928126d 100644 (file)
@@ -1628,7 +1628,7 @@ static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
        if (host->version < SDHCI_SPEC_300)
                return 0;
 
-       if (host->quirks & SDHCI_QUIRK_NON_STD_VOLTAGE_SWITCHING) {
+       if (host->quirks2 & SDHCI_QUIRK2_NON_STD_VOLTAGE_SWITCHING) {
                if (host->ops->switch_signal_voltage)
                        return host->ops->switch_signal_voltage(
                                host, ios->signal_voltage);
@@ -1751,7 +1751,7 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
        disable_irq(host->irq);
        spin_lock(&host->lock);
 
-       if ((host->quirks & SDHCI_QUIRK_NON_STANDARD_TUNING) &&
+       if ((host->quirks2 & SDHCI_QUIRK2_NON_STANDARD_TUNING) &&
                host->ops->execute_freq_tuning) {
                err = host->ops->execute_freq_tuning(host, opcode);
                spin_unlock(&host->lock);
@@ -2948,7 +2948,7 @@ int sdhci_add_host(struct sdhci_host *host)
        if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
                host->timeout_clk = mmc->f_max / 1000;
 
-       if (!(host->quirks & SDHCI_QUIRK_NO_CALC_MAX_DISCARD_TO))
+       if (!(host->quirks2 & SDHCI_QUIRK2_NO_CALC_MAX_DISCARD_TO))
                mmc->max_discard_to = (1 << 27) / host->timeout_clk;
 
        if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
index 03afc94..398770e 100644 (file)
@@ -22,84 +22,84 @@ struct sdhci_host {
        /* Data set by hardware interface driver */
        const char *hw_name;    /* Hardware bus name */
 
-       u64 quirks;     /* Deviations from spec. */
+       u32 quirks;     /* Deviations from spec. */
 
 /* Controller doesn't honor resets unless we touch the clock register */
-#define SDHCI_QUIRK_CLOCK_BEFORE_RESET                 (1ULL<<0)
+#define SDHCI_QUIRK_CLOCK_BEFORE_RESET                 (1<<0)
 /* Controller has bad caps bits, but really supports DMA */
-#define SDHCI_QUIRK_FORCE_DMA                          (1ULL<<1)
+#define SDHCI_QUIRK_FORCE_DMA                          (1<<1)
 /* Controller doesn't like to be reset when there is no card inserted. */
-#define SDHCI_QUIRK_NO_CARD_NO_RESET                   (1ULL<<2)
+#define SDHCI_QUIRK_NO_CARD_NO_RESET                   (1<<2)
 /* Controller doesn't like clearing the power reg before a change */
-#define SDHCI_QUIRK_SINGLE_POWER_WRITE                 (1ULL<<3)
+#define SDHCI_QUIRK_SINGLE_POWER_WRITE                 (1<<3)
 /* Controller has flaky internal state so reset it on each ios change */
-#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS              (1ULL<<4)
+#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS              (1<<4)
 /* Controller has an unusable DMA engine */
-#define SDHCI_QUIRK_BROKEN_DMA                         (1ULL<<5)
+#define SDHCI_QUIRK_BROKEN_DMA                         (1<<5)
 /* Controller has an unusable ADMA engine */
-#define SDHCI_QUIRK_BROKEN_ADMA                                (1ULL<<6)
+#define SDHCI_QUIRK_BROKEN_ADMA                                (1<<6)
 /* Controller can only DMA from 32-bit aligned addresses */
-#define SDHCI_QUIRK_32BIT_DMA_ADDR                     (1ULL<<7)
+#define SDHCI_QUIRK_32BIT_DMA_ADDR                     (1<<7)
 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
-#define SDHCI_QUIRK_32BIT_DMA_SIZE                     (1ULL<<8)
+#define SDHCI_QUIRK_32BIT_DMA_SIZE                     (1<<8)
 /* Controller can only ADMA chunks that are a multiple of 32 bits */
-#define SDHCI_QUIRK_32BIT_ADMA_SIZE                    (1ULL<<9)
+#define SDHCI_QUIRK_32BIT_ADMA_SIZE                    (1<<9)
 /* Controller needs to be reset after each request to stay stable */
-#define SDHCI_QUIRK_RESET_AFTER_REQUEST                        (1ULL<<10)
+#define SDHCI_QUIRK_RESET_AFTER_REQUEST                        (1<<10)
 /* Controller needs voltage and power writes to happen separately */
-#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER            (1ULL<<11)
+#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER            (1<<11)
 /* Controller provides an incorrect timeout value for transfers */
-#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL                 (1ULL<<12)
+#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL                 (1<<12)
 /* Controller has an issue with buffer bits for small transfers */
-#define SDHCI_QUIRK_BROKEN_SMALL_PIO                   (1ULL<<13)
+#define SDHCI_QUIRK_BROKEN_SMALL_PIO                   (1<<13)
 /* Controller does not provide transfer-complete interrupt when not busy */
-#define SDHCI_QUIRK_NO_BUSY_IRQ                                (1ULL<<14)
+#define SDHCI_QUIRK_NO_BUSY_IRQ                                (1<<14)
 /* Controller has unreliable card detection */
-#define SDHCI_QUIRK_BROKEN_CARD_DETECTION              (1ULL<<15)
+#define SDHCI_QUIRK_BROKEN_CARD_DETECTION              (1<<15)
 /* Controller reports inverted write-protect state */
-#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT             (1ULL<<16)
+#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT             (1<<16)
 /* Controller has nonstandard clock management */
-#define SDHCI_QUIRK_NONSTANDARD_CLOCK                  (1ULL<<17)
+#define SDHCI_QUIRK_NONSTANDARD_CLOCK                  (1<<17)
 /* Controller does not like fast PIO transfers */
-#define SDHCI_QUIRK_PIO_NEEDS_DELAY                    (1ULL<<18)
+#define SDHCI_QUIRK_PIO_NEEDS_DELAY                    (1<<18)
 /* Controller losing signal/interrupt enable states after reset */
-#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET           (1ULL<<19)
+#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET           (1<<19)
 /* Controller has to be forced to use block size of 2048 bytes */
-#define SDHCI_QUIRK_FORCE_BLK_SZ_2048                  (1ULL<<20)
+#define SDHCI_QUIRK_FORCE_BLK_SZ_2048                  (1<<20)
 /* Controller cannot do multi-block transfers */
-#define SDHCI_QUIRK_NO_MULTIBLOCK                      (1ULL<<21)
+#define SDHCI_QUIRK_NO_MULTIBLOCK                      (1<<21)
 /* Controller can only handle 1-bit data transfers */
-#define SDHCI_QUIRK_FORCE_1_BIT_DATA                   (1ULL<<22)
+#define SDHCI_QUIRK_FORCE_1_BIT_DATA                   (1<<22)
 /* Controller needs 10ms delay between applying power and clock */
-#define SDHCI_QUIRK_DELAY_AFTER_POWER                  (1ULL<<23)
+#define SDHCI_QUIRK_DELAY_AFTER_POWER                  (1<<23)
 /* Controller uses SDCLK instead of TMCLK for data timeouts */
-#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK            (1ULL<<24)
+#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK            (1<<24)
 /* Controller reports wrong base clock capability */
-#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN              (1ULL<<25)
+#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN              (1<<25)
 /* Controller cannot support End Attribute in NOP ADMA descriptor */
-#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC              (1ULL<<26)
+#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC              (1<<26)
 /* Controller is missing device caps. Use caps provided by host */
-#define SDHCI_QUIRK_MISSING_CAPS                       (1ULL<<27)
+#define SDHCI_QUIRK_MISSING_CAPS                       (1<<27)
 /* Controller uses Auto CMD12 command to stop the transfer */
-#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12             (1ULL<<28)
+#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12             (1<<28)
 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
-#define SDHCI_QUIRK_NO_HISPD_BIT                       (1ULL<<29)
+#define SDHCI_QUIRK_NO_HISPD_BIT                       (1<<29)
 /* Controller treats ADMA descriptors with length 0000h incorrectly */
-#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC           (1ULL<<30)
+#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC           (1<<30)
 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
-#define SDHCI_QUIRK_UNSTABLE_RO_DETECT                 (1ULL<<31)
-/* Controller cannot report the line status in present state register */
-#define SDHCI_QUIRK_NON_STD_VOLTAGE_SWITCHING          (1ULL<<32)
-/* Controller doesn't follow the standard frequency tuning procedure */
-#define SDHCI_QUIRK_NON_STANDARD_TUNING                (1ULL<<33)
-/* Controller doesn't calculate max_discard_to */
-#define SDHCI_QUIRK_NO_CALC_MAX_DISCARD_TO             (1ULL<<34)
+#define SDHCI_QUIRK_UNSTABLE_RO_DETECT                 (1<<31)
 
        unsigned int quirks2;   /* More deviations from spec. */
 
 #define SDHCI_QUIRK2_HOST_OFF_CARD_ON                  (1<<0)
 /* Controller has incorrect preset values */
 #define SDHCI_QUIRK2_BROKEN_PRESET_VALUES              (1<<1)
+/* Controller cannot report the line status in present state register */
+#define SDHCI_QUIRK2_NON_STD_VOLTAGE_SWITCHING         (1<<2)
+/* Controller doesn't follow the standard frequency tuning procedure */
+#define SDHCI_QUIRK2_NON_STANDARD_TUNING               (1<<3)
+/* Controller doesn't calculate max_discard_to */
+#define SDHCI_QUIRK2_NO_CALC_MAX_DISCARD_TO            (1<<4)
 
        int irq;                /* Device IRQ */
        void __iomem *ioaddr;   /* Mapped address */