ARM: tegra: clock: Update parameterized cluster switch
Varun Wadekar [Wed, 11 Apr 2012 05:56:27 +0000 (10:56 +0530)]
Adjusted CPU rate during parametrized (enforced from sysfs) cluster
switch, so that target rate meets min/max constraints on both sides
of the switch. Updated local timer rate accordingly.

Bug 945975

(cherry picked from commit c27f5a2e7380cb667f1f6a4ba61daf67c63ef2d4)

Change-Id: I130ec1a32ecaf8adfd7eff1ec2042f569b54ac54
Reviewed-on: http://git-master/r/90805

Conflicts:

arch/arm/mach-tegra/tegra3_clocks.c

Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

arch/arm/mach-tegra/tegra30_clocks.c
dmesg.txt [new file with mode: 0644]

index 8a0dec8..d4b8800 100644 (file)
@@ -1047,15 +1047,20 @@ static int tegra3_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p)
        spin_unlock(&parameters_lock);
 
        if (flags) {
-               /* over-clocking after the switch - allow, but lower rate */
-               if (rate > p->max_rate) {
-                       rate = p->max_rate;
+               /* over/under-clocking after switch - allow, but update rate */
+               if ((rate > p->max_rate) || (rate < p->min_rate)) {
+                       unsigned long fl;
+
+                       rate = rate > p->max_rate ? p->max_rate : p->min_rate;
                        ret = clk_set_rate(c->parent, rate);
                        if (ret) {
                                pr_err("%s: Failed to set rate %lu for %s\n",
                                        __func__, rate, p->name);
                                return ret;
                        }
+                       clk_lock_save(c->parent, &fl);
+                       clk_set_rate(&tegra3_clk_twd, clk_get_rate_locked(c->parent));
+                       clk_unlock_restore(c->parent, &fl);
                }
        } else
 #endif
diff --git a/dmesg.txt b/dmesg.txt
new file mode 100644 (file)
index 0000000..e69de29