powerpc/perf_events: Fix priority of MSR HV vs PR bits
Michael Neuling [Wed, 14 Oct 2009 19:32:15 +0000 (19:32 +0000)]
The architecture defines that if MSR PR is set we are in problem state
irrespective of the HV bit.  This fixes perf events to reflect this.

Also, on bare metal systems, samples taken in Linux will now be reported
as kernel rather than hypervisor.

Signed-off-by: Michael Neuling <mikey@neuling.org>
CC: paulus@samba.org
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

arch/powerpc/kernel/perf_event.c

index bbcbae1..87f1663 100644 (file)
@@ -116,20 +116,23 @@ static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp)
 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
 {
        unsigned long mmcra = regs->dsisr;
+       unsigned long sihv = MMCRA_SIHV;
+       unsigned long sipr = MMCRA_SIPR;
 
        if (TRAP(regs) != 0xf00)
                return 0;       /* not a PMU interrupt */
 
        if (ppmu->flags & PPMU_ALT_SIPR) {
-               if (mmcra & POWER6_MMCRA_SIHV)
-                       return PERF_RECORD_MISC_HYPERVISOR;
-               return (mmcra & POWER6_MMCRA_SIPR) ?
-                       PERF_RECORD_MISC_USER : PERF_RECORD_MISC_KERNEL;
+               sihv = POWER6_MMCRA_SIHV;
+               sipr = POWER6_MMCRA_SIPR;
        }
-       if (mmcra & MMCRA_SIHV)
+
+       /* PR has priority over HV, so order below is important */
+       if (mmcra & sipr)
+               return PERF_RECORD_MISC_USER;
+       if ((mmcra & sihv) && (freeze_events_kernel != MMCR0_FCHV))
                return PERF_RECORD_MISC_HYPERVISOR;
-       return (mmcra & MMCRA_SIPR) ? PERF_RECORD_MISC_USER :
-               PERF_RECORD_MISC_KERNEL;
+       return PERF_RECORD_MISC_KERNEL;
 }
 
 /*