drm/radeon/kms: vram sizing on certain r100 chips needs workaround.
Dave Airlie [Tue, 21 Jul 2009 10:39:30 +0000 (20:39 +1000)]
If an rn50/r100/m6/m7 GPU has < 64MB RAM, i.e. 8/16/32, the
aperture used to calculate the MC_FB_LOCATION needs to be worked
out from the CONFIG_APER_SIZE register, and not the actual vram size.

TTM VRAM size was also being initialised wrong, use actual vram size
to initialise it.

Signed-off-by: Dave Airlie <airlied@redhat.com>

12 files changed:
drivers/gpu/drm/radeon/r100.c
drivers/gpu/drm/radeon/r520.c
drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_device.c
drivers/gpu/drm/radeon/radeon_gem.c
drivers/gpu/drm/radeon/radeon_ttm.c
drivers/gpu/drm/radeon/rs400.c
drivers/gpu/drm/radeon/rs600.c
drivers/gpu/drm/radeon/rs690.c
drivers/gpu/drm/radeon/rv515.c
drivers/gpu/drm/radeon/rv770.c

index 0e00fef..05a4489 100644 (file)
@@ -173,8 +173,12 @@ void r100_mc_setup(struct radeon_device *rdev)
                DRM_ERROR("Failed to register debugfs file for R100 MC !\n");
        }
        /* Write VRAM size in case we are limiting it */
-       WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
-       tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
+       WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
+       /* Novell bug 204882 for RN50/M6/M7 with 8/16/32MB VRAM,
+        * if the aperture is 64MB but we have 32MB VRAM
+        * we report only 32MB VRAM but we have to set MC_FB_LOCATION
+        * to 64MB, otherwise the gpu accidentially dies */
+       tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
        tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
        tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
        WREG32(RADEON_MC_FB_LOCATION, tmp);
@@ -1447,25 +1451,28 @@ void r100_vram_init_sizes(struct radeon_device *rdev)
                uint32_t tom;
                /* read NB_TOM to get the amount of ram stolen for the GPU */
                tom = RREG32(RADEON_NB_TOM);
-               rdev->mc.vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
+               rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
                /* for IGPs we need to keep VRAM where it was put by the BIOS */
                rdev->mc.vram_location = (tom & 0xffff) << 16;
-               WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
+               WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
+               rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
        } else {
-               rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
+               rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
                /* Some production boards of m6 will report 0
                 * if it's 8 MB
                 */
-               if (rdev->mc.vram_size == 0) {
-                       rdev->mc.vram_size = 8192 * 1024;
-                       WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
+               if (rdev->mc.real_vram_size == 0) {
+                       rdev->mc.real_vram_size = 8192 * 1024;
+                       WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
                }
                /* let driver place VRAM */
                rdev->mc.vram_location = 0xFFFFFFFFUL;
                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 
                  * Novell bug 204882 + along with lots of ubuntu ones */
-               if (config_aper_size > rdev->mc.vram_size)
-                       rdev->mc.vram_size = config_aper_size;
+               if (config_aper_size > rdev->mc.real_vram_size)
+                       rdev->mc.mc_vram_size = config_aper_size;
+               else
+                       rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
        }
 
        /* work out accessible VRAM */
@@ -1477,8 +1484,11 @@ void r100_vram_init_sizes(struct radeon_device *rdev)
        if (accessible > rdev->mc.aper_size)
                accessible = rdev->mc.aper_size;
 
-       if (rdev->mc.vram_size > rdev->mc.aper_size)
-               rdev->mc.vram_size = rdev->mc.aper_size;
+       if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
+               rdev->mc.mc_vram_size = rdev->mc.aper_size;
+
+       if (rdev->mc.real_vram_size > rdev->mc.aper_size)
+               rdev->mc.real_vram_size = rdev->mc.aper_size;
 }
 
 void r100_vram_info(struct radeon_device *rdev)
index 0a981e2..09fb0b6 100644 (file)
@@ -95,8 +95,8 @@ int r520_mc_init(struct radeon_device *rdev)
                       "programming pipes. Bad things might happen.\n");
        }
        /* Write VRAM size in case we are limiting it */
-       WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
-       tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
+       WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
+       tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
        tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16);
        tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16);
        WREG32_MC(R520_MC_FB_LOCATION, tmp);
index c45559f..538cd90 100644 (file)
@@ -67,7 +67,7 @@ int r600_mc_init(struct radeon_device *rdev)
                       "programming pipes. Bad things might happen.\n");
        }
 
-       tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
+       tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
        tmp = REG_SET(R600_MC_FB_TOP, tmp >> 24);
        tmp |= REG_SET(R600_MC_FB_BASE, rdev->mc.vram_location >> 24);
        WREG32(R600_MC_VM_FB_LOCATION, tmp);
@@ -140,7 +140,8 @@ void r600_vram_get_type(struct radeon_device *rdev)
 void r600_vram_info(struct radeon_device *rdev)
 {
        r600_vram_get_type(rdev);
-       rdev->mc.vram_size = RREG32(R600_CONFIG_MEMSIZE);
+       rdev->mc.real_vram_size = RREG32(R600_CONFIG_MEMSIZE);
+       rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 
        /* Could aper size report 0 ? */
        rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
index 63a3fe3..045b33b 100644 (file)
@@ -332,8 +332,11 @@ struct radeon_mc {
        unsigned                gtt_location;
        unsigned                gtt_size;
        unsigned                vram_location;
-       unsigned                vram_size;
+       /* for some chips with <= 32MB we need to lie
+        * about vram size near mc fb location */
+       unsigned                mc_vram_size;
        unsigned                vram_width;
+       unsigned                real_vram_size;
        int                     vram_mtrr;
        bool                    vram_is_ddr;
 };
index f78db5c..6d1749e 100644 (file)
@@ -121,7 +121,7 @@ int radeon_mc_setup(struct radeon_device *rdev)
        if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
                /* vram location was already setup try to put gtt after
                 * if it fits */
-               tmp = rdev->mc.vram_location + rdev->mc.vram_size;
+               tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
                tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
                if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
                        rdev->mc.gtt_location = tmp;
@@ -136,13 +136,13 @@ int radeon_mc_setup(struct radeon_device *rdev)
        } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
                /* gtt location was already setup try to put vram before
                 * if it fits */
-               if (rdev->mc.vram_size < rdev->mc.gtt_location) {
+               if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
                        rdev->mc.vram_location = 0;
                } else {
                        tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
-                       tmp += (rdev->mc.vram_size - 1);
-                       tmp &= ~(rdev->mc.vram_size - 1);
-                       if ((0xFFFFFFFFUL - tmp) >= rdev->mc.vram_size) {
+                       tmp += (rdev->mc.mc_vram_size - 1);
+                       tmp &= ~(rdev->mc.mc_vram_size - 1);
+                       if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
                                rdev->mc.vram_location = tmp;
                        } else {
                                printk(KERN_ERR "[drm] vram too big to fit "
@@ -152,12 +152,14 @@ int radeon_mc_setup(struct radeon_device *rdev)
                }
        } else {
                rdev->mc.vram_location = 0;
-               rdev->mc.gtt_location = rdev->mc.vram_size;
+               rdev->mc.gtt_location = rdev->mc.mc_vram_size;
        }
-       DRM_INFO("radeon: VRAM %uM\n", rdev->mc.vram_size >> 20);
+       DRM_INFO("radeon: VRAM %uM\n", rdev->mc.real_vram_size >> 20);
        DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
                 rdev->mc.vram_location,
-                rdev->mc.vram_location + rdev->mc.vram_size - 1);
+                rdev->mc.vram_location + rdev->mc.mc_vram_size - 1);
+       if (rdev->mc.real_vram_size != rdev->mc.mc_vram_size)
+               DRM_INFO("radeon: VRAM less than aperture workaround enabled\n");
        DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20);
        DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
                 rdev->mc.gtt_location,
@@ -573,7 +575,7 @@ int radeon_device_init(struct radeon_device *rdev,
        rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
                                      MTRR_TYPE_WRCOMB, 1);
        DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n",
-                rdev->mc.vram_size >> 20,
+                rdev->mc.real_vram_size >> 20,
                 (unsigned)rdev->mc.aper_size >> 20);
        DRM_INFO("RAM width %dbits %cDR\n",
                 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
index 1254208..cded518 100644 (file)
@@ -157,9 +157,9 @@ int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
        struct radeon_device *rdev = dev->dev_private;
        struct drm_radeon_gem_info *args = data;
 
-       args->vram_size = rdev->mc.vram_size;
+       args->vram_size = rdev->mc.real_vram_size;
        /* FIXME: report somethings that makes sense */
-       args->vram_visible = rdev->mc.vram_size - (4 * 1024 * 1024);
+       args->vram_visible = rdev->mc.real_vram_size - (4 * 1024 * 1024);
        args->gart_size = rdev->mc.gtt_size;
        return 0;
 }
index f3469b9..15c3531 100644 (file)
@@ -454,7 +454,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
                return r;
        }
        r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, 0,
-                          ((rdev->mc.aper_size) >> PAGE_SHIFT));
+                          ((rdev->mc.real_vram_size) >> PAGE_SHIFT));
        if (r) {
                DRM_ERROR("Failed initializing VRAM heap.\n");
                return r;
@@ -471,7 +471,7 @@ int radeon_ttm_init(struct radeon_device *rdev)
                return r;
        }
        DRM_INFO("radeon: %uM of VRAM memory ready\n",
-                rdev->mc.vram_size / (1024 * 1024));
+                rdev->mc.real_vram_size / (1024 * 1024));
        r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 0,
                           ((rdev->mc.gtt_size) >> PAGE_SHIFT));
        if (r) {
index 96a3c84..b29affd 100644 (file)
@@ -233,7 +233,7 @@ int rs400_mc_init(struct radeon_device *rdev)
 
        rs400_gpu_init(rdev);
        rs400_gart_disable(rdev);
-       rdev->mc.gtt_location = rdev->mc.vram_size;
+       rdev->mc.gtt_location = rdev->mc.mc_vram_size;
        rdev->mc.gtt_location += (rdev->mc.gtt_size - 1);
        rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1);
        r = radeon_mc_setup(rdev);
@@ -247,7 +247,7 @@ int rs400_mc_init(struct radeon_device *rdev)
                       "programming pipes. Bad things might happen.\n");
        }
 
-       tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
+       tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
        tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
        tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
        WREG32(RADEON_MC_FB_LOCATION, tmp);
index bccdce7..bbea6de 100644 (file)
@@ -223,7 +223,7 @@ int rs600_mc_init(struct radeon_device *rdev)
                printk(KERN_WARNING "Failed to wait MC idle while "
                       "programming pipes. Bad things might happen.\n");
        }
-       tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
+       tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
        tmp = REG_SET(RS600_MC_FB_TOP, tmp >> 16);
        tmp |= REG_SET(RS600_MC_FB_START, rdev->mc.vram_location >> 16);
        WREG32_MC(RS600_MC_FB_LOCATION, tmp);
index 97eaee3..839595b 100644 (file)
@@ -67,7 +67,7 @@ int rs690_mc_init(struct radeon_device *rdev)
        rs400_gart_disable(rdev);
 
        /* Setup GPU memory space */
-       rdev->mc.gtt_location = rdev->mc.vram_size;
+       rdev->mc.gtt_location = rdev->mc.mc_vram_size;
        rdev->mc.gtt_location += (rdev->mc.gtt_size - 1);
        rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1);
        rdev->mc.vram_location = 0xFFFFFFFFUL;
@@ -82,7 +82,7 @@ int rs690_mc_init(struct radeon_device *rdev)
                printk(KERN_WARNING "Failed to wait MC idle while "
                       "programming pipes. Bad things might happen.\n");
        }
-       tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
+       tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
        tmp = REG_SET(RS690_MC_FB_TOP, tmp >> 16);
        tmp |= REG_SET(RS690_MC_FB_START, rdev->mc.vram_location >> 16);
        WREG32_MC(RS690_MCCFG_FB_LOCATION, tmp);
@@ -228,7 +228,8 @@ void rs690_vram_info(struct radeon_device *rdev)
        } else {
                rdev->mc.vram_width = 64;
        }
-       rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
+       rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
+       rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
 
        rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
        rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
index 4fd4118..551e608 100644 (file)
@@ -100,10 +100,10 @@ int rv515_mc_init(struct radeon_device *rdev)
                       "programming pipes. Bad things might happen.\n");
        }
        /* Write VRAM size in case we are limiting it */
-       WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
+       WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
        tmp = REG_SET(MC_FB_START, rdev->mc.vram_location >> 16);
        WREG32(0x134, tmp);
-       tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
+       tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
        tmp = REG_SET(MC_FB_TOP, tmp >> 16);
        tmp |= REG_SET(MC_FB_START, rdev->mc.vram_location >> 16);
        WREG32_MC(MC_FB_LOCATION, tmp);
@@ -369,10 +369,7 @@ void rv515_vram_info(struct radeon_device *rdev)
        fixed20_12 a;
 
        rv515_vram_get_type(rdev);
-       rdev->mc.vram_size = RREG32(CONFIG_MEMSIZE);
 
-       rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
-       rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
        /* FIXME: we should enforce default clock in case GPU is not in
         * default setup
         */
index da50cc5..21d8ffd 100644 (file)
@@ -67,7 +67,7 @@ int rv770_mc_init(struct radeon_device *rdev)
                       "programming pipes. Bad things might happen.\n");
        }
 
-       tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
+       tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
        tmp = REG_SET(R700_MC_FB_TOP, tmp >> 24);
        tmp |= REG_SET(R700_MC_FB_BASE, rdev->mc.vram_location >> 24);
        WREG32(R700_MC_VM_FB_LOCATION, tmp);