ARM: tegra: pcie: set mselect to 204MHz for Tegra3
Peter Daifuku [Mon, 29 Apr 2013 20:20:29 +0000 (13:20 -0700)]
When PCI is enabled, increase mselect from 102MHz to 204MHz for improved PCIE x4 bandwidth

In tegra_update_mselect_rate, when PCI is enabled, set mselect to CPU rate up to 204MHz.

Bug 1014125
Bug 1035617
Bug 1293381

Change-Id: Ia23f26a82276638bd1d414f4a0c6456fe282f906
Signed-off-by: Naveen Kumar S<nkumars@nvidia.com>
Reviewed-on: http://git-master/r/225327
(cherry picked from commit 559aed0bbe3fd859c48464fa7289c1d82256bfb5)
Reviewed-on: http://git-master/r/232971
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

arch/arm/mach-tegra/common.c
arch/arm/mach-tegra/tegra30_clocks.c

index 255b1ec..5c644af 100644 (file)
@@ -317,7 +317,11 @@ static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
        { "sbc4.sclk",  NULL,           40000000,       false},
        { "sbc5.sclk",  NULL,           40000000,       false},
        { "sbc6.sclk",  NULL,           40000000,       false},
+#ifdef CONFIG_TEGRA_PCI
+       { "mselect",    "pll_p",        204000000,      true },
+#else
        { "mselect",    "pll_p",        102000000,      true },
+#endif
        { NULL,         NULL,           0,              0},
 };
 static __initdata struct tegra_clk_init_table tegra30_cbus_init_table[] = {
index 7887a02..11972bf 100644 (file)
@@ -4410,8 +4410,11 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("pcie",      "tegra-pcie",           "pcie", 70,     0,      250000000, mux_clk_m,                   0),
        PERIPH_CLK("afi",       "tegra-pcie",           "afi",  72,     0,      250000000, mux_clk_m,                   0),
        PERIPH_CLK("se",        "se",                   NULL,   127,    0x42c,  625000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB),
+#ifdef CONFIG_TEGRA_PCI
+       PERIPH_CLK("mselect",   "mselect",              NULL,   99,     0x3b4,  204000000, mux_pllp_clkm,               MUX | DIV_U71),
+#else
        PERIPH_CLK("mselect",   "mselect",              NULL,   99,     0x3b4,  108000000, mux_pllp_clkm,               MUX | DIV_U71),
-
+#endif
        SHARED_CLK("avp.sclk",  "tegra-avp",            "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("bsea.sclk", "tegra-aes",            "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("usbd.sclk", "tegra-udc.0",          "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
@@ -4962,11 +4965,19 @@ int tegra_update_mselect_rate(unsigned long cpu_rate)
                        return -ENODEV;
        }
 
+#ifdef CONFIG_TEGRA_PCI
+       /* Vote on mselect frequency based on cpu frequency:
+          keep mselect at cpu rate up to 204 MHz;
+          cpu rate is in kHz, mselect rate is in Hz */
+       mselect_rate = cpu_rate * 1000;
+       mselect_rate = min(mselect_rate, 204000000UL);
+#else
        /* Vote on mselect frequency based on cpu frequency:
           keep mselect at half of cpu rate up to 102 MHz;
           cpu rate is in kHz, mselect rate is in Hz */
        mselect_rate = DIV_ROUND_UP(cpu_rate, 2) * 1000;
        mselect_rate = min(mselect_rate, 102000000UL);
+#endif
 
        if (mselect_rate != clk_get_rate(mselect))
                return clk_set_rate(mselect, mselect_rate);