ARM: tegra30: pm: flush L1 data before exit coherency on secondary CPU
Varun Wadekar [Tue, 27 Mar 2012 10:47:20 +0000 (15:47 +0530)]
Change-Id: Ib16ee5efdf8686d750a5263baa8fff4d258e68cd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/92542
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arch/arm/mach-tegra/sleep-t3.S

index 6d58585..caabeb7 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/include/mach/sleep-t3.S
  *
- * Copyright (c) 2010-2011, NVIDIA Corporation.
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -235,6 +235,16 @@ ENDPROC(tegra3_sleep_core_finish)
  */
 ENTRY(tegra3_sleep_cpu_secondary_finish)
        mov     r6, lr
+
+       dsb
+#ifdef MULTI_CACHE
+       mov32   r10, cpu_cache
+       mov     lr, pc
+       ldr     pc, [r10, #CACHE_FLUSH_KERN_ALL]
+#else
+       bl      __cpuc_flush_kern_all
+#endif
+
        bl      tegra_cpu_exit_coherency
 
        /* Powergate this CPU. */