ARM: tegra: cardhu: add mem 437MHz table for Samsung K4P8G304EB
Jihoon Bang [Wed, 11 Jul 2012 18:06:40 +0000 (11:06 -0700)]
Bug 1005576

Signed-off-by: Peter Zu <pzu@nvidia.com>
Reviewed-on: http://git-master/r/112036
(cherry picked from commit 1f1e6d22e771336fb9e0b91bbabf12fa89f0c57c)

Change-Id: If65aba6aaa0a400c960a2d2b1315a07fa44dcefe
Reviewed-on: http://git-master/r/115054
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arch/arm/mach-tegra/board-cardhu-memory.c

index 1a2b164..4694417 100644 (file)
@@ -4226,6 +4226,246 @@ static const struct tegra_emc_table cardhu_emc_tables_k4p8g304eb[] = {
        },
        {
                0x32,       /* Rev 3.2 */
+               266500,     /* SDRAM frequency */
+               {
+                       0x0000000f, /* EMC_RC */
+                       0x00000022, /* EMC_RFC */
+                       0x0000000b, /* EMC_RAS */
+                       0x00000004, /* EMC_RP */
+                       0x00000005, /* EMC_R2W */
+                       0x00000005, /* EMC_W2R */
+                       0x00000001, /* EMC_R2P */
+                       0x00000007, /* EMC_W2P */
+                       0x00000004, /* EMC_RD_RCD */
+                       0x00000004, /* EMC_WR_RCD */
+                       0x00000002, /* EMC_RRD */
+                       0x00000002, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000002, /* EMC_WDV */
+                       0x00000005, /* EMC_QUSE */
+                       0x00000002, /* EMC_QRST */
+                       0x0000000c, /* EMC_QSAFE */
+                       0x0000000b, /* EMC_RDV */
+                       0x000003ef, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x000000fb, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000001, /* EMC_PDEX2WR */
+                       0x00000001, /* EMC_PDEX2RD */
+                       0x00000004, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000001, /* EMC_AR2PDEN */
+                       0x00000009, /* EMC_RW2PDEN */
+                       0x00000026, /* EMC_TXSR */
+                       0x00000026, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x0000000e, /* EMC_TFAW */
+                       0x00000006, /* EMC_TRPAB */
+                       0x00000001, /* EMC_TCLKSTABLE */
+                       0x00000002, /* EMC_TCLKSTOP */
+                       0x00000455, /* EMC_TREFBW */
+                       0x00000000, /* EMC_QUSE_EXTRA */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x00006282, /* EMC_FBIO_CFG5 */
+                       0x003200a4, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00060000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00060000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x00068000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00068000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00068000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00068000, /* EMC_DLL_XFORM_DQ3 */
+                       0x000a0220, /* EMC_XM2CMDPADCTRL */
+                       0x0800003d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc004, /* EMC_XM2CLKPADCTRL */
+                       0x01f1f008, /* EMC_XM2COMPPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x08000068, /* EMC_XM2QUSEPADCTRL */
+                       0x08000000, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00064000, /* EMC_ZCAL_INTERVAL */
+                       0x00000060, /* EMC_ZCAL_WAIT_CNT */
+                       0x000a000a, /* EMC_MRS_WAIT_CNT */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x800008ee, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x00000004, /* MC_EMEM_ARB_CFG */
+                       0x80000030, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x03030001, /* MC_EMEM_ARB_DA_TURNS */
+                       0x00090608, /* MC_EMEM_ARB_DA_COVERS */
+                       0x70040c09, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0xe0000000, /* EMC_FBIO_SPARE */
+                       0xff00ff00, /* EMC_CFG_RSV */
+               },
+               0x00000018, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000001, /* EMC_CFG.PERIODIC_QRST */
+               0x00000000, /* Mode Register 0 */
+               0x00010042, /* Mode Register 1 */
+               0x00020002, /* Mode Register 2 */
+               0x00000000, /* EMC_CFG.DYN_SELF_REF */
+       },
+       {
+               0x32,       /* Rev 3.2 */
+               437000,     /* SDRAM frequency */
+               {
+                       0x0000001a, /* EMC_RC */
+                       0x00000038, /* EMC_RFC */
+                       0x00000012, /* EMC_RAS */
+                       0x00000007, /* EMC_RP */
+                       0x00000007, /* EMC_R2W */
+                       0x00000009, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x0000000c, /* EMC_W2P */
+                       0x00000007, /* EMC_RD_RCD */
+                       0x00000007, /* EMC_WR_RCD */
+                       0x00000004, /* EMC_RRD */
+                       0x00000002, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000004, /* EMC_WDV */
+                       0x00000008, /* EMC_QUSE */
+                       0x00000005, /* EMC_QRST */
+                       0x0000000d, /* EMC_QSAFE */
+                       0x0000000f, /* EMC_RDV */
+                       0x00000674, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x0000019d, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000003, /* EMC_PDEX2WR */
+                       0x00000003, /* EMC_PDEX2RD */
+                       0x00000007, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000001, /* EMC_AR2PDEN */
+                       0x0000000d, /* EMC_RW2PDEN */
+                       0x0000003e, /* EMC_TXSR */
+                       0x0000003e, /* EMC_TXSRDLL */
+                       0x00000007, /* EMC_TCKE */
+                       0x00000016, /* EMC_TFAW */
+                       0x0000000a, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000002, /* EMC_TCLKSTOP */
+                       0x0000071a, /* EMC_TREFBW */
+                       0x00000000, /* EMC_QUSE_EXTRA */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x00006282, /* EMC_FBIO_CFG5 */
+                       0x00190084, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00014000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00014000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00014000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00014000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00014000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00014000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00014000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00014000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x00038000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00038000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00038000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00038000, /* EMC_DLL_XFORM_DQ3 */
+                       0x00080220, /* EMC_XM2CMDPADCTRL */
+                       0x0800003d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffe004, /* EMC_XM2CLKPADCTRL */
+                       0x01f1f408, /* EMC_XM2COMPPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x08000068, /* EMC_XM2QUSEPADCTRL */
+                       0x08000000, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00064000, /* EMC_ZCAL_INTERVAL */
+                       0x0000009e, /* EMC_ZCAL_WAIT_CNT */
+                       0x000d000d, /* EMC_MRS_WAIT_CNT */
+                       0xa0f10202, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80000dff, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x00000006, /* MC_EMEM_ARB_CFG */
+                       0xc000004f, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RP */
+                       0x0000000d, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x05040001, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000e090d, /* MC_EMEM_ARB_DA_COVERS */
+                       0x7027140e, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0xe0000000, /* EMC_FBIO_SPARE */
+                       0xff00ff88, /* EMC_CFG_RSV */
+               },
+               0x00000028, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000001, /* EMC_CFG.PERIODIC_QRST */
+               0x00000000, /* Mode Register 0 */
+               0x000100a2, /* Mode Register 1 */
+               0x00020005, /* Mode Register 2 */
+               0x00000000, /* EMC_CFG.DYN_SELF_REF */
+       },
+       {
+               0x32,       /* Rev 3.2 */
                533000,     /* SDRAM frequency */
                {
                        0x0000001f, /* EMC_RC */