m68knommu: fix clock rate value reported for ColdFire 54xx parts
Greg Ungerer [Tue, 2 Nov 2010 07:40:37 +0000 (17:40 +1000)]
The instruction timings of the ColdFire 54xx family parts are
different to other version 4 parts (or version 2 or 3 parts for
that matter too).

Move the instruction timing setting into the ColdFire part
specific headers, and set the 54xx value appropriately.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

12 files changed:
arch/m68k/include/asm/m5206sim.h
arch/m68k/include/asm/m520xsim.h
arch/m68k/include/asm/m523xsim.h
arch/m68k/include/asm/m5249sim.h
arch/m68k/include/asm/m5272sim.h
arch/m68k/include/asm/m527xsim.h
arch/m68k/include/asm/m528xsim.h
arch/m68k/include/asm/m5307sim.h
arch/m68k/include/asm/m532xsim.h
arch/m68k/include/asm/m5407sim.h
arch/m68k/include/asm/m54xxsim.h
arch/m68knommu/kernel/setup.c

index 6cc7a42..b882a21 100644 (file)
@@ -12,7 +12,8 @@
 #define        m5206sim_h
 /****************************************************************************/
 
-#define        CPU_NAME        "COLDFIRE(m5206)"
+#define        CPU_NAME                "COLDFIRE(m5206)"
+#define        CPU_INSTR_PER_JIFFY     3
 
 /*
  *     Define the 5206 SIM register set addresses.
index afa2118..85b39ed 100644 (file)
@@ -11,7 +11,8 @@
 #define m520xsim_h
 /****************************************************************************/
 
-#define        CPU_NAME        "COLDFIRE(m520x)"
+#define        CPU_NAME                "COLDFIRE(m520x)"
+#define        CPU_INSTR_PER_JIFFY     3
 
 /*
  *  Define the 520x SIM register set addresses.
index 6a2c90d..9d597dc 100644 (file)
@@ -11,7 +11,8 @@
 #define        m523xsim_h
 /****************************************************************************/
 
-#define        CPU_NAME        "COLDFIRE(m523x)"
+#define        CPU_NAME                "COLDFIRE(m523x)"
+#define        CPU_INSTR_PER_JIFFY     3
 
 /*
  *     Define the 523x SIM register set addresses.
index 6c49ed8..c107228 100644 (file)
@@ -11,7 +11,8 @@
 #define        m5249sim_h
 /****************************************************************************/
 
-#define        CPU_NAME        "COLDFIRE(m5249)"
+#define        CPU_NAME                "COLDFIRE(m5249)"
+#define        CPU_INSTR_PER_JIFFY     3
 
 /*
  *     Define the 5249 SIM register set addresses.
index 7edef8f..8cea714 100644 (file)
@@ -12,7 +12,8 @@
 #define        m5272sim_h
 /****************************************************************************/
 
-#define        CPU_NAME        "COLDFIRE(m5272)"
+#define        CPU_NAME                "COLDFIRE(m5272)"
+#define        CPU_INSTR_PER_JIFFY     3
 
 /*
  *     Define the 5272 SIM register set addresses.
index 627156a..5223b71 100644 (file)
@@ -11,7 +11,8 @@
 #define        m527xsim_h
 /****************************************************************************/
 
-#define        CPU_NAME        "COLDFIRE(m527x)"
+#define        CPU_NAME                "COLDFIRE(m527x)"
+#define        CPU_INSTR_PER_JIFFY     3
 
 
 /*
index 03a6d57..4e35f97 100644 (file)
@@ -11,7 +11,8 @@
 #define        m528xsim_h
 /****************************************************************************/
 
-#define        CPU_NAME        "COLDFIRE(m528x)"
+#define        CPU_NAME                "COLDFIRE(m528x)"
+#define        CPU_INSTR_PER_JIFFY     3
 
 /*
  *     Define the 5280/5282 SIM register set addresses.
index 3e06b83..008f36b 100644 (file)
@@ -14,7 +14,8 @@
 #define        m5307sim_h
 /****************************************************************************/
 
-#define        CPU_NAME        "COLDFIRE(m5307)"
+#define        CPU_NAME                "COLDFIRE(m5307)"
+#define        CPU_INSTR_PER_JIFFY     3
 
 /*
  *     Define the 5307 SIM register set addresses.
index 9f4688b..b8126d3 100644 (file)
@@ -9,7 +9,8 @@
 #define        m532xsim_h
 /****************************************************************************/
 
-#define        CPU_NAME        "COLDFIRE(m532x)"
+#define        CPU_NAME                "COLDFIRE(m532x)"
+#define        CPU_INSTR_PER_JIFFY     3
 
 #define MCF_REG32(x) (*(volatile unsigned long  *)(x))
 #define MCF_REG16(x) (*(volatile unsigned short *)(x))
index 1de44c5..e07d4d8 100644 (file)
@@ -14,7 +14,8 @@
 #define        m5407sim_h
 /****************************************************************************/
 
-#define        CPU_NAME        "COLDFIRE(m5407)"
+#define        CPU_NAME                "COLDFIRE(m5407)"
+#define        CPU_INSTR_PER_JIFFY     3
 
 /*
  *     Define the 5407 SIM register set addresses.
index d69a64f..6072248 100644 (file)
@@ -5,9 +5,10 @@
 #ifndef        m54xxsim_h
 #define m54xxsim_h
 
-#define        CPU_NAME        "COLDFIRE(m54xx)"
+#define        CPU_NAME                "COLDFIRE(m54xx)"
+#define        CPU_INSTR_PER_JIFFY     2
 
-#define MCFINT_VECBASE      64
+#define MCFINT_VECBASE         64
 
 /*
  *      Interrupt Controller Registers
index f48d9df..5c931f9 100644 (file)
@@ -66,13 +66,20 @@ void (*mach_power_off)(void);
 #ifdef CONFIG_M68360
 #define CPU_NAME       "MC68360"
 #endif
-/*
- * The ColdFire CPU names are defined in their headers.
- */
 #ifndef CPU_NAME
 #define        CPU_NAME        "UNKNOWN"
 #endif
 
+/*
+ * Different cores have different instruction execution timings.
+ * The old/traditional 68000 cores are basically all the same, at 16.
+ * The ColdFire cores vary a little, their values are defined in their
+ * headers. We default to the standard 68000 value here.
+ */
+#ifndef CPU_INSTR_PER_JIFFY
+#define        CPU_INSTR_PER_JIFFY     16
+#endif
+
 extern int _stext, _etext, _sdata, _edata, _sbss, _ebss, _end;
 extern int _ramstart, _ramend;
 
@@ -273,12 +280,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
        cpu = CPU_NAME;
        mmu = "none";
        fpu = "none";
-
-#ifdef CONFIG_COLDFIRE
-       clockfreq = (loops_per_jiffy * HZ) * 3;
-#else
-       clockfreq = (loops_per_jiffy * HZ) * 16;
-#endif
+       clockfreq = (loops_per_jiffy * HZ) * CPU_INSTR_PER_JIFFY;
 
        seq_printf(m, "CPU:\t\t%s\n"
                      "MMU:\t\t%s\n"