ARM: tegra11: clock: Add latency entry to EMC DFS table
Alex Frid [Thu, 6 Dec 2012 20:44:26 +0000 (12:44 -0800)]
Bug 1189313

Change-Id: I4e39647c0c4702f05f03ecd00c82aa568f5fedf6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/169138
(cherry picked from commit 265d1a86a3d288d5b59cd2ab8e73cdbb03c706f3)
Reviewed-on: http://git-master/r/171623
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

arch/arm/mach-tegra/tegra11_emc.c
include/linux/platform_data/tegra_emc.h

index 843e106..c45c2dd 100644 (file)
@@ -980,6 +980,7 @@ static int init_emc_table(const struct tegra11_emc_table *table, int table_size)
        tegra_emc_table_size = min(table_size, TEGRA_EMC_TABLE_MAX_SIZE);
        switch (table[0].rev) {
        case 0x40:
+       case 0x41:
                start_timing.burst_regs_num = table[0].burst_regs_num;
                start_timing.emc_trimmers_num = table[0].emc_trimmers_num;
                break;
index 3b06f78..59a061e 100644 (file)
@@ -94,6 +94,7 @@ struct tegra11_emc_table {
        u32 emc_mode_1;
        u32 emc_mode_2;
        u32 emc_mode_4;
+       u32 clock_change_latency;
 };
 
 struct tegra11_emc_pdata {