ARM: tegra11: clock: Add EMC DPD control to EMC DFS
Alex Frid [Sun, 24 Mar 2013 05:44:14 +0000 (22:44 -0700)]
Added EMC_SEL_DPD_CTRL register to the list of burst registers updated
during EMC clock rate change. Increased EMC DFS table revision to 4.2.

Bug 1259481

Change-Id: I5b46fefdadfd8f4cbe0f56de0a9e0eaeecf6a1c5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/212385
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

arch/arm/mach-tegra/tegra11_emc.c

index ba9140d..7544d9a 100644 (file)
@@ -166,7 +166,8 @@ enum {
        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DA_TURNS),        \
        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DA_COVERS),       \
        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_MISC0),           \
-       DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_RING1_THROTTLE),
+       DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_RING1_THROTTLE),  \
+       DEFINE_REG(TEGRA_EMC_BASE, EMC_SEL_DPD_CTRL),
 
 #define BURST_UP_DOWN_REG_LIST \
        DEFINE_REG(TEGRA_MC_BASE, MC_PTSA_GRANT_DECREMENT),     \
@@ -1068,6 +1069,7 @@ static int init_emc_table(const struct tegra11_emc_table *table, int table_size)
        switch (table[0].rev) {
        case 0x40:
        case 0x41:
+       case 0x42:
                start_timing.burst_regs_num = table[0].burst_regs_num;
                start_timing.emc_trimmers_num = table[0].emc_trimmers_num;
                break;