Merge tag 'boards' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Linus Torvalds [Mon, 9 Jan 2012 22:37:41 +0000 (14:37 -0800)]
Board-level changes

This adds and extends support for specific boards on a number of
ARM platforms:  omap, imx, samsung, tegra, ...

* tag 'boards' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (49 commits)
  Enable 32 bit flash support for iMX21ADS board
  ARM: mx31pdk: Add MC13783 RTC support
  iomux-mx25: configuration to support CSPI3 on CSI pins
  MX1:apf9328: Add i2c support
  mioa701: add newly available DoC G3 chip
  arm/tegra: remove __initdata annotation from pinmux tables
  arm/tegra: Use bus notifiers to trigger pinmux setup
  arm/tegra: Refactor board-*-pinmux.c to share code
  arm/tegra: Fix mistake in Trimslice's pinmux
  arm/tegra: Rework Seaboard-vs-Ventana pinmux table
  arm/tegra: Remove useless entries from ventana_pinmux[]
  arm/tegra: PCIe: Remove include of mach/pinmux.h
  arm/tegra: Harmony PCIe: Don't touch pinmux
  arm/tegra: Add AUXDATA for tegra-pinmux and tegra-gpio
  arm/tegra: Split Seaboard GPIO table to allow for Ventana
  ARM: imx6q: generate imx6q dtb files
  arm/imx6q: Rename Sabreauto to Armadillo2
  arm/imx6q-sabrelite: add enet phy ksz9021rn fixup
  arm/imx6: add imx6q sabrelite board support
  dts/imx: rename uart labels to consistent with hw spec
  ...

1  2 
arch/arm/mach-s3c64xx/Kconfig
arch/arm/mach-s3c64xx/mach-crag6410.c
arch/arm/mach-s3c64xx/pm.c
arch/arm/mach-tegra/board-dt-tegra20.c

@@@ -8,7 -8,6 +8,7 @@@ config PLAT_S3C64X
        bool
        depends on ARCH_S3C64XX
        select SAMSUNG_WAKEMASK
 +      select PM_GENERIC_DOMAINS
        default y
        help
          Base platform code for any Samsung S3C64XX device
@@@ -194,7 -193,7 +194,7 @@@ config SMDK6410_WM1190_EV
        depends on MACH_SMDK6410
        select REGULATOR
        select REGULATOR_WM8350
-       select S3C24XX_GPIO_EXTRA64
+       select SAMSUNG_GPIO_EXTRA64
        select MFD_WM8350_I2C
        select MFD_WM8350_CONFIG_MODE_0
        select MFD_WM8350_CONFIG_MODE_3
@@@ -212,7 -211,7 +212,7 @@@ config SMDK6410_WM1192_EV
        depends on MACH_SMDK6410
        select REGULATOR
        select REGULATOR_WM831X
-       select S3C24XX_GPIO_EXTRA64
+       select SAMSUNG_GPIO_EXTRA64
        select MFD_WM831X
        select MFD_WM831X_I2C
        help
@@@ -294,7 -293,7 +294,7 @@@ config MACH_WLF_CRAGG_641
        select S3C_DEV_WDT
        select S3C_DEV_RTC
        select S3C64XX_DEV_SPI0
-       select S3C24XX_GPIO_EXTRA128
+       select SAMSUNG_GPIO_EXTRA128
        select I2C
        help
          Machine support for the Wolfson Cragganmore S3C6410 variant.
@@@ -37,6 -37,8 +37,8 @@@
  #include <linux/mfd/wm831x/irq.h>
  #include <linux/mfd/wm831x/gpio.h>
  
+ #include <sound/wm1250-ev1.h>
  #include <asm/hardware/vic.h>
  #include <asm/mach/arch.h>
  #include <asm/mach-types.h>
@@@ -289,6 -291,11 +291,11 @@@ static struct platform_device speyside_
        .id             = -1,
  };
  
+ static struct platform_device littlemill_device = {
+       .name           = "littlemill",
+       .id             = -1,
+ };
  static struct regulator_consumer_supply wallvdd_consumers[] = {
        REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
        REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
@@@ -341,6 -348,7 +348,7 @@@ static struct platform_device *crag6410
        &crag6410_backlight_device,
        &speyside_device,
        &speyside_wm8962_device,
+       &littlemill_device,
        &lowland_device,
        &wallvdd_device,
  };
@@@ -374,6 -382,10 +382,10 @@@ static struct regulator_init_data vddar
        .driver_data = &vddarm_pdata,
  };
  
+ static struct regulator_consumer_supply vddint_consumers[] __initdata = {
+       REGULATOR_SUPPLY("vddint", NULL),
+ };
  static struct regulator_init_data vddint __initdata = {
        .constraints = {
                .name = "VDDINT",
                .always_on = 1,
                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
        },
+       .num_consumer_supplies = ARRAY_SIZE(vddint_consumers),
+       .consumer_supplies = vddint_consumers,
+       .supply_regulator = "WALLVDD",
  };
  
  static struct regulator_init_data vddmem __initdata = {
@@@ -502,7 -517,8 +517,8 @@@ static struct wm831x_touch_pdata touch_
  static struct wm831x_pdata crag_pmic_pdata __initdata = {
        .wm831x_num = 1,
        .irq_base = BANFF_PMIC_IRQ_BASE,
-       .gpio_base = GPIO_BOARD_START + 8,
+       .gpio_base = BANFF_PMIC_GPIO_BASE,
+       .soft_shutdown = true,
  
        .backup = &banff_backup_pdata,
  
@@@ -607,6 -623,7 +623,7 @@@ static struct wm831x_pdata glenfarclas_
        .wm831x_num = 2,
        .irq_base = GLENFARCLAS_PMIC_IRQ_BASE,
        .gpio_base = GLENFARCLAS_PMIC_GPIO_BASE,
+       .soft_shutdown = true,
  
        .gpio_defaults = {
                /* GPIO1-3: IRQ inputs, rising edge triggered, CMOS */
        .disable_touch = true,
  };
  
+ static struct wm1250_ev1_pdata wm1250_ev1_pdata = {
+       .gpios = {
+               [WM1250_EV1_GPIO_CLK_ENA] = S3C64XX_GPN(12),
+               [WM1250_EV1_GPIO_CLK_SEL0] = S3C64XX_GPL(12),
+               [WM1250_EV1_GPIO_CLK_SEL1] = S3C64XX_GPL(13),
+               [WM1250_EV1_GPIO_OSR] = S3C64XX_GPL(14),
+               [WM1250_EV1_GPIO_MASTER] = S3C64XX_GPL(8),
+       },
+ };
  static struct i2c_board_info i2c_devs1[] __initdata = {
        { I2C_BOARD_INFO("wm8311", 0x34),
          .irq = S3C_EINT(0),
        { I2C_BOARD_INFO("wlf-gf-module", 0x25) },
        { I2C_BOARD_INFO("wlf-gf-module", 0x26) },
  
-       { I2C_BOARD_INFO("wm1250-ev1", 0x27) },
+       { I2C_BOARD_INFO("wm1250-ev1", 0x27),
+         .platform_data = &wm1250_ev1_pdata },
+ };
+ static struct s3c2410_platform_i2c i2c1_pdata = {
+       .frequency = 400000,
+       .bus_num = 1,
  };
  
  static void __init crag6410_map_io(void)
@@@ -694,7 -727,7 +727,7 @@@ static void __init crag6410_machine_ini
        s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata);
  
        s3c_i2c0_set_platdata(&i2c0_pdata);
-       s3c_i2c1_set_platdata(NULL);
+       s3c_i2c1_set_platdata(&i2c1_pdata);
        s3c_fb_set_platdata(&crag6410_lcd_pdata);
  
        i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
  
        regulator_has_full_constraints();
  
 -      s3c_pm_init();
 +      s3c64xx_pm_init();
  }
  
  MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
  #include <linux/serial_core.h>
  #include <linux/io.h>
  #include <linux/gpio.h>
 +#include <linux/pm_domain.h>
  
  #include <mach/map.h>
  #include <mach/irqs.h>
  
 +#include <plat/devs.h>
  #include <plat/pm.h>
  #include <plat/wakeup-mask.h>
  
  #include <mach/regs-gpio-memport.h>
  #include <mach/regs-modem.h>
  
 +struct s3c64xx_pm_domain {
 +      char *const name;
 +      u32 ena;
 +      u32 pwr_stat;
 +      struct generic_pm_domain pd;
 +};
 +
 +static int s3c64xx_pd_off(struct generic_pm_domain *domain)
 +{
 +      struct s3c64xx_pm_domain *pd;
 +      u32 val;
 +
 +      pd = container_of(domain, struct s3c64xx_pm_domain, pd);
 +
 +      val = __raw_readl(S3C64XX_NORMAL_CFG);
 +      val &= ~(pd->ena);
 +      __raw_writel(val, S3C64XX_NORMAL_CFG);
 +
 +      return 0;
 +}
 +
 +static int s3c64xx_pd_on(struct generic_pm_domain *domain)
 +{
 +      struct s3c64xx_pm_domain *pd;
 +      u32 val;
 +      long retry = 1000000L;
 +
 +      pd = container_of(domain, struct s3c64xx_pm_domain, pd);
 +
 +      val = __raw_readl(S3C64XX_NORMAL_CFG);
 +      val |= pd->ena;
 +      __raw_writel(val, S3C64XX_NORMAL_CFG);
 +
 +      /* Not all domains provide power status readback */
 +      if (pd->pwr_stat) {
 +              do {
 +                      cpu_relax();
 +                      if (__raw_readl(S3C64XX_BLK_PWR_STAT) & pd->pwr_stat)
 +                              break;
 +              } while (retry--);
 +
 +              if (!retry) {
 +                      pr_err("Failed to start domain %s\n", pd->name);
 +                      return -EBUSY;
 +              }
 +      }
 +
 +      return 0;
 +}
 +
 +static struct s3c64xx_pm_domain s3c64xx_pm_irom = {
 +      .name = "IROM",
 +      .ena = S3C64XX_NORMALCFG_IROM_ON,
 +      .pd = {
 +              .power_off = s3c64xx_pd_off,
 +              .power_on = s3c64xx_pd_on,
 +      },
 +};
 +
 +static struct s3c64xx_pm_domain s3c64xx_pm_etm = {
 +      .name = "ETM",
 +      .ena = S3C64XX_NORMALCFG_DOMAIN_ETM_ON,
 +      .pwr_stat = S3C64XX_BLKPWRSTAT_ETM,
 +      .pd = {
 +              .power_off = s3c64xx_pd_off,
 +              .power_on = s3c64xx_pd_on,
 +      },
 +};
 +
 +static struct s3c64xx_pm_domain s3c64xx_pm_s = {
 +      .name = "S",
 +      .ena = S3C64XX_NORMALCFG_DOMAIN_S_ON,
 +      .pwr_stat = S3C64XX_BLKPWRSTAT_S,
 +      .pd = {
 +              .power_off = s3c64xx_pd_off,
 +              .power_on = s3c64xx_pd_on,
 +      },
 +};
 +
 +static struct s3c64xx_pm_domain s3c64xx_pm_f = {
 +      .name = "F",
 +      .ena = S3C64XX_NORMALCFG_DOMAIN_F_ON,
 +      .pwr_stat = S3C64XX_BLKPWRSTAT_F,
 +      .pd = {
 +              .power_off = s3c64xx_pd_off,
 +              .power_on = s3c64xx_pd_on,
 +      },
 +};
 +
 +static struct s3c64xx_pm_domain s3c64xx_pm_p = {
 +      .name = "P",
 +      .ena = S3C64XX_NORMALCFG_DOMAIN_P_ON,
 +      .pwr_stat = S3C64XX_BLKPWRSTAT_P,
 +      .pd = {
 +              .power_off = s3c64xx_pd_off,
 +              .power_on = s3c64xx_pd_on,
 +      },
 +};
 +
 +static struct s3c64xx_pm_domain s3c64xx_pm_i = {
 +      .name = "I",
 +      .ena = S3C64XX_NORMALCFG_DOMAIN_I_ON,
 +      .pwr_stat = S3C64XX_BLKPWRSTAT_I,
 +      .pd = {
 +              .power_off = s3c64xx_pd_off,
 +              .power_on = s3c64xx_pd_on,
 +      },
 +};
 +
 +static struct s3c64xx_pm_domain s3c64xx_pm_g = {
 +      .name = "G",
 +      .ena = S3C64XX_NORMALCFG_DOMAIN_G_ON,
 +      .pd = {
 +              .power_off = s3c64xx_pd_off,
 +              .power_on = s3c64xx_pd_on,
 +      },
 +};
 +
 +static struct s3c64xx_pm_domain s3c64xx_pm_v = {
 +      .name = "V",
 +      .ena = S3C64XX_NORMALCFG_DOMAIN_V_ON,
 +      .pwr_stat = S3C64XX_BLKPWRSTAT_V,
 +      .pd = {
 +              .power_off = s3c64xx_pd_off,
 +              .power_on = s3c64xx_pd_on,
 +      },
 +};
 +
 +static struct s3c64xx_pm_domain *s3c64xx_always_on_pm_domains[] = {
 +      &s3c64xx_pm_irom,
 +};
 +
 +static struct s3c64xx_pm_domain *s3c64xx_pm_domains[] = {
 +      &s3c64xx_pm_etm,
 +      &s3c64xx_pm_g,
 +      &s3c64xx_pm_v,
 +      &s3c64xx_pm_i,
 +      &s3c64xx_pm_p,
 +      &s3c64xx_pm_s,
 +      &s3c64xx_pm_f,
 +};
 +
  #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
  void s3c_pm_debug_smdkled(u32 set, u32 clear)
  {
@@@ -325,31 -181,25 +325,44 @@@ static void s3c64xx_pm_prepare(void
        __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
  }
  
 -static int s3c64xx_pm_init(void)
 +int __init s3c64xx_pm_init(void)
 +{
 +      int i;
 +
 +      s3c_pm_init();
 +
 +      for (i = 0; i < ARRAY_SIZE(s3c64xx_always_on_pm_domains); i++)
 +              pm_genpd_init(&s3c64xx_always_on_pm_domains[i]->pd,
 +                            &pm_domain_always_on_gov, false);
 +
 +      for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++)
 +              pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false);
 +
 +      if (dev_get_platdata(&s3c_device_fb.dev))
 +              pm_genpd_add_device(&s3c64xx_pm_f.pd, &s3c_device_fb.dev);
 +
 +      return 0;
 +}
 +
 +static __init int s3c64xx_pm_initcall(void)
  {
+       u32 val;
        pm_cpu_prep = s3c64xx_pm_prepare;
        pm_cpu_sleep = s3c64xx_cpu_suspend;
        pm_uart_udivslot = 1;
  
+       /*
+        * Unconditionally disable power domains that contain only
+        * blocks which have no mainline driver support.
+        */
+       val = __raw_readl(S3C64XX_NORMAL_CFG);
+       val &= ~(S3C64XX_NORMALCFG_DOMAIN_G_ON |
+                S3C64XX_NORMALCFG_DOMAIN_V_ON |
+                S3C64XX_NORMALCFG_DOMAIN_I_ON |
+                S3C64XX_NORMALCFG_DOMAIN_P_ON);
+       __raw_writel(val, S3C64XX_NORMAL_CFG);
  #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
        gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
        gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");
  
        return 0;
  }
 +arch_initcall(s3c64xx_pm_initcall);
  
 -arch_initcall(s3c64xx_pm_init);
 +static __init int s3c64xx_pm_late_initcall(void)
 +{
 +      pm_genpd_poweroff_unused();
 +
 +      return 0;
 +}
 +late_initcall(s3c64xx_pm_late_initcall);
@@@ -54,6 -54,8 +54,8 @@@ void trimslice_pinmux_init(void)
  void ventana_pinmux_init(void);
  
  struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
+       OF_DEV_AUXDATA("nvidia,tegra20-pinmux", TEGRA_APB_MISC_BASE + 0x14, "tegra-pinmux", NULL),
+       OF_DEV_AUXDATA("nvidia,tegra20-gpio", TEGRA_GPIO_BASE, "tegra-gpio", NULL),
        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
@@@ -61,7 -63,7 +63,7 @@@
        OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", NULL),
        OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL),
        OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL),
 -      OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_DVC_BASE, "tegra-i2c.3", NULL),
 +      OF_DEV_AUXDATA("nvidia,tegra20-i2c-dvc", TEGRA_DVC_BASE, "tegra-i2c.3", NULL),
        OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.0", NULL),
        OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra-i2s.1", NULL),
        OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra-das", NULL),
@@@ -110,13 -112,6 +112,6 @@@ static void __init tegra_dt_init(void
  
        tegra_clk_init_from_table(tegra_dt_clk_init_table);
  
-       /*
-        * Finished with the static registrations now; fill in the missing
-        * devices
-        */
-       of_platform_populate(NULL, tegra_dt_match_table,
-                               tegra20_auxdata_lookup, NULL);
        for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) {
                if (of_machine_is_compatible(pinmux_configs[i].machine)) {
                        pinmux_configs[i].init();
  
        WARN(i == ARRAY_SIZE(pinmux_configs),
                "Unknown platform! Pinmuxing not initialized\n");
+       /*
+        * Finished with the static registrations now; fill in the missing
+        * devices
+        */
+       of_platform_populate(NULL, tegra_dt_match_table,
+                               tegra20_auxdata_lookup, NULL);
  }
  
  static const char *tegra20_dt_board_compat[] = {