ARM: tegra11: clock: Remove PLLC2/C3 from Host1x Mux
Alex Frid [Sun, 17 Mar 2013 04:04:50 +0000 (21:04 -0700)]
Since on Tegra11 Host1x is no longer belong to cbus, removed PLLC2/C3
inputs from Host1x clock source multiplexer definition.

Change-Id: Ib0656c922f8a938d71a81f328b01c76a368164c2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/210235
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

arch/arm/mach-tegra/tegra11_clocks.c

index 4e46722..13efbc2 100644 (file)
@@ -6677,7 +6677,7 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK_EX("msenc",  "msenc",                NULL,   91,     0x1f0,  600000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT, &tegra_msenc_clk_ops),
 #endif
        PERIPH_CLK("tsec",      "tsec",                 NULL,   83,     0x1f4,  600000000, mux_pllp_pllc2_c_c3_pllm_clkm,       MUX | MUX8 | DIV_U71 | DIV_U71_INT),
-       PERIPH_CLK("host1x",    "host1x",               NULL,   28,     0x180,  384000000, mux_pllm_pllc2_c_c3_pllp_plla,       MUX | MUX8 | DIV_U71 | DIV_U71_INT),
+       PERIPH_CLK("host1x",    "host1x",               NULL,   28,     0x180,  384000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT),
        PERIPH_CLK_EX("dtv",    "dtv",                  NULL,   79,     0x1dc,  250000000, mux_clk_m,                   PERIPH_ON_APB,  &tegra_dtv_clk_ops),
        PERIPH_CLK("hdmi",      "hdmi",                 NULL,   51,     0x18c,  297000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8 | DIV_U71),
        PERIPH_CLK("disp1",     "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8),