drm/i915: add some barriers when changing DIPs
Paulo Zanoni [Mon, 28 May 2012 19:43:00 +0000 (16:43 -0300)]
commit 9d9740f099f2eaf309c4c9cbc0d732507140db28 upstream.

On IVB and older, we basically have two registers: the control and the
data register. We write a few consecutitve times to the control
register, and we need these writes to arrive exactly in the specified
order.

Also, when we're changing the data register, we need to guarantee that
anything written to the control register already arrived (since
changing the control register can change where the data register
points to). Also, we need to make sure all the writes to the data
register happen exactly in the specified order, and we also *can't*
read the data register during this process, since reading and/or
writing it will change the place it points to.

So invoke the "better safe than sorry" rule and just be careful and
put barriers everywhere :)

On HSW we still have a control register that we write many times, but
we have many data registers.

Demanded-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
[bwh: Backported to 3.2:
 - There are only two write_infoframe functions to be modified
 - The other VIDEO_DIP_CTL writes are in entirely different functions]
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Signed-off-by: Julien Cristau <jcristau@debian.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

drivers/gpu/drm/i915/intel_hdmi.c

index fb44e9d..c60100d 100644 (file)
@@ -138,14 +138,17 @@ static void i9xx_write_infoframe(struct drm_encoder *encoder,
 
        I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags);
 
+       mmiowb();
        for (i = 0; i < len; i += 4) {
                I915_WRITE(VIDEO_DIP_DATA, *data);
                data++;
        }
+       mmiowb();
 
        flags |= intel_infoframe_flags(frame);
 
        I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags);
+       POSTING_READ(VIDEO_DIP_CTL);
 }
 
 static void ironlake_write_infoframe(struct drm_encoder *encoder,
@@ -168,14 +171,17 @@ static void ironlake_write_infoframe(struct drm_encoder *encoder,
 
        I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
 
+       mmiowb();
        for (i = 0; i < len; i += 4) {
                I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
                data++;
        }
+       mmiowb();
 
        flags |= intel_infoframe_flags(frame);
 
        I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
+       POSTING_READ(reg);
 }
 static void intel_set_infoframe(struct drm_encoder *encoder,
                                struct dip_infoframe *frame)
@@ -549,10 +555,13 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
        if (!HAS_PCH_SPLIT(dev)) {
                intel_hdmi->write_infoframe = i9xx_write_infoframe;
                I915_WRITE(VIDEO_DIP_CTL, 0);
+               POSTING_READ(VIDEO_DIP_CTL);
        } else {
                intel_hdmi->write_infoframe = ironlake_write_infoframe;
-               for_each_pipe(i)
+               for_each_pipe(i) {
                        I915_WRITE(TVIDEO_DIP_CTL(i), 0);
+                       POSTING_READ(TVIDEO_DIP_CTL(i));
+               }
        }
 
        drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);