Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik...
Linus Torvalds [Sat, 29 Oct 2005 18:25:16 +0000 (11:25 -0700)]
81 files changed:
MAINTAINERS
drivers/net/Kconfig
drivers/net/Makefile
drivers/net/acenic.c
drivers/net/amd8111e.c [changed mode: 0755->0644]
drivers/net/amd8111e.h [changed mode: 0755->0644]
drivers/net/au1000_eth.c
drivers/net/b44.c
drivers/net/bmac.c
drivers/net/bnx2.c
drivers/net/e1000/e1000_ethtool.c
drivers/net/e1000/e1000_main.c
drivers/net/eepro.c
drivers/net/fs_enet/Kconfig [new file with mode: 0644]
drivers/net/fs_enet/Makefile [new file with mode: 0644]
drivers/net/fs_enet/fs_enet-main.c [new file with mode: 0644]
drivers/net/fs_enet/fs_enet-mii.c [new file with mode: 0644]
drivers/net/fs_enet/fs_enet.h [new file with mode: 0644]
drivers/net/fs_enet/mac-fcc.c [new file with mode: 0644]
drivers/net/fs_enet/mac-fec.c [new file with mode: 0644]
drivers/net/fs_enet/mac-scc.c [new file with mode: 0644]
drivers/net/fs_enet/mii-bitbang.c [new file with mode: 0644]
drivers/net/fs_enet/mii-fixed.c [new file with mode: 0644]
drivers/net/hamradio/mkiss.c
drivers/net/ibm_emac/Makefile
drivers/net/ibm_emac/ibm_emac.h
drivers/net/ibm_emac/ibm_emac_core.c
drivers/net/ibm_emac/ibm_emac_core.h
drivers/net/ibm_emac/ibm_emac_debug.c
drivers/net/ibm_emac/ibm_emac_debug.h [new file with mode: 0644]
drivers/net/ibm_emac/ibm_emac_mal.c
drivers/net/ibm_emac/ibm_emac_mal.h
drivers/net/ibm_emac/ibm_emac_phy.c
drivers/net/ibm_emac/ibm_emac_phy.h
drivers/net/ibm_emac/ibm_emac_rgmii.c [new file with mode: 0644]
drivers/net/ibm_emac/ibm_emac_rgmii.h
drivers/net/ibm_emac/ibm_emac_tah.c [new file with mode: 0644]
drivers/net/ibm_emac/ibm_emac_tah.h
drivers/net/ibm_emac/ibm_emac_zmii.c [new file with mode: 0644]
drivers/net/ibm_emac/ibm_emac_zmii.h
drivers/net/ibmveth.c
drivers/net/ibmveth.h
drivers/net/irda/donauboe.c
drivers/net/irda/irda-usb.c
drivers/net/irda/irport.c
drivers/net/irda/sir_dev.c
drivers/net/irda/vlsi_ir.c
drivers/net/mace.c
drivers/net/ne2k-pci.c
drivers/net/ni65.c
drivers/net/pcmcia/pcnet_cs.c
drivers/net/rrunner.c
drivers/net/s2io.c
drivers/net/saa9730.c
drivers/net/sis190.c
drivers/net/sis900.c
drivers/net/smc91x.c
drivers/net/starfire.c
drivers/net/sundance.c
drivers/net/tg3.c
drivers/net/tg3.h
drivers/net/tulip/de2104x.c
drivers/net/tulip/tulip_core.c
drivers/net/via-velocity.c
drivers/net/wireless/airo.c
drivers/net/wireless/airo_cs.c
drivers/net/wireless/atmel.c
drivers/net/wireless/atmel_cs.c
drivers/net/wireless/hermes.c
drivers/net/wireless/hermes.h
drivers/net/wireless/hostap/hostap_ioctl.c
drivers/net/wireless/ipw2200.c
drivers/net/wireless/orinoco.c
drivers/net/wireless/prism54/islpci_dev.c
drivers/net/wireless/prism54/islpci_eth.c
drivers/net/wireless/prism54/oid_mgt.c
drivers/net/wireless/strip.c
include/linux/fs_enet_pd.h [new file with mode: 0644]
include/linux/pci_ids.h
include/net/ax25.h
include/net/netrom.h

index 770155a..251a28e 100644 (file)
@@ -1945,6 +1945,14 @@ M:       george@mvista.com
 L:     netdev@vger.kernel.org
 S:     Supported
 
+POWERPC 4xx EMAC DRIVER
+P:     Eugene Surovegin
+M:     ebs@ebshome.net
+W:     http://kernel.ebshome.net/emac/
+L:     linuxppc-embedded@ozlabs.org
+L:     netdev@vger.kernel.org
+S:     Maintained
+
 PNP SUPPORT
 P:     Adam Belay
 M:     ambx1@neo.rr.com
index fee8c5c..6d4f9ce 100644 (file)
@@ -1163,38 +1163,74 @@ config IBMVETH
          be called ibmveth.
 
 config IBM_EMAC
-       bool "IBM PPC4xx EMAC driver support"
+       tristate "PowerPC 4xx on-chip Ethernet support"
        depends on 4xx
-       select CRC32
-       ---help---
-         This driver supports the IBM PPC4xx EMAC family of on-chip
-         Ethernet controllers.
-
-config IBM_EMAC_ERRMSG
-       bool "Verbose error messages"
-       depends on IBM_EMAC && BROKEN
+       help
+         This driver supports the PowerPC 4xx EMAC family of on-chip
+          Ethernet controllers.
 
 config IBM_EMAC_RXB
        int "Number of receive buffers"
        depends on IBM_EMAC
-       default "128" if IBM_EMAC4
-       default "64"
+       default "128"
 
 config IBM_EMAC_TXB
        int "Number of transmit buffers"
        depends on IBM_EMAC
-       default "128" if IBM_EMAC4
-       default "8"
+       default "64"
+
+config IBM_EMAC_POLL_WEIGHT
+       int "MAL NAPI polling weight"
+       depends on IBM_EMAC
+       default "32"
 
-config IBM_EMAC_FGAP
-       int "Frame gap"
+config IBM_EMAC_RX_COPY_THRESHOLD
+       int "RX skb copy threshold (bytes)"
        depends on IBM_EMAC
-       default "8"
+       default "256"
 
-config IBM_EMAC_SKBRES
-       int "Skb reserve amount"
+config IBM_EMAC_RX_SKB_HEADROOM
+       int "Additional RX skb headroom (bytes)"
        depends on IBM_EMAC
        default "0"
+       help
+         Additional receive skb headroom. Note, that driver
+         will always reserve at least 2 bytes to make IP header
+         aligned, so usualy there is no need to add any additional
+         headroom.
+         
+         If unsure, set to 0.
+
+config IBM_EMAC_PHY_RX_CLK_FIX
+       bool "PHY Rx clock workaround"
+       depends on IBM_EMAC && (405EP || 440GX || 440EP)
+       help
+         Enable this if EMAC attached to a PHY which doesn't generate
+         RX clock if there is no link, if this is the case, you will 
+         see "TX disable timeout" or "RX disable timeout" in the system
+         log.
+         
+         If unsure, say N.
+
+config IBM_EMAC_DEBUG
+       bool "Debugging"
+       depends on IBM_EMAC
+       default n
+
+config IBM_EMAC_ZMII
+       bool
+       depends on IBM_EMAC && (NP405H || NP405L || 44x)
+       default y
+
+config IBM_EMAC_RGMII
+       bool
+       depends on IBM_EMAC && 440GX
+       default y
+               
+config IBM_EMAC_TAH
+       bool
+       depends on IBM_EMAC && 440GX
+       default y
 
 config NET_PCI
        bool "EISA, VLB, PCI and on board controllers"
@@ -1775,6 +1811,7 @@ config NE_H8300
          controller on the Renesas H8/300 processor.
 
 source "drivers/net/fec_8xx/Kconfig"
+source "drivers/net/fs_enet/Kconfig"
 
 endmenu
 
@@ -2201,8 +2238,8 @@ config S2IO
        depends on PCI
        ---help---
          This driver supports the 10Gbe XFrame NIC of S2IO. 
-         For help regarding driver compilation, installation and 
-         tuning please look into ~/drivers/net/s2io/README.txt.
+         More specific information on configuring the driver is in 
+         <file:Documentation/networking/s2io.txt>.
 
 config S2IO_NAPI
        bool "Use Rx Polling (NAPI) (EXPERIMENTAL)"
index 1a84e04..7c313cb 100644 (file)
@@ -203,3 +203,6 @@ obj-$(CONFIG_IRDA) += irda/
 obj-$(CONFIG_ETRAX_ETHERNET) += cris/
 
 obj-$(CONFIG_NETCONSOLE) += netconsole.o
+
+obj-$(CONFIG_FS_ENET) += fs_enet/
+
index dbecc6b..b8953de 100644 (file)
@@ -871,10 +871,8 @@ static void ace_init_cleanup(struct net_device *dev)
        if (ap->info)
                pci_free_consistent(ap->pdev, sizeof(struct ace_info),
                                    ap->info, ap->info_dma);
-       if (ap->skb)
-               kfree(ap->skb);
-       if (ap->trace_buf)
-               kfree(ap->trace_buf);
+       kfree(ap->skb);
+       kfree(ap->trace_buf);
 
        if (dev->irq)
                free_irq(dev->irq, dev);
old mode 100755 (executable)
new mode 100644 (file)
old mode 100755 (executable)
new mode 100644 (file)
index 7850691..332e995 100644 (file)
@@ -1606,8 +1606,7 @@ err_out:
        /* here we should have a valid dev plus aup-> register addresses
         * so we can reset the mac properly.*/
        reset_mac(dev);
-       if (aup->mii)
-               kfree(aup->mii);
+       kfree(aup->mii);
        for (i = 0; i < NUM_RX_DMA; i++) {
                if (aup->rx_db_inuse[i])
                        ReleaseDB(aup, aup->rx_db_inuse[i]);
@@ -1806,8 +1805,7 @@ static void __exit au1000_cleanup_module(void)
                if (dev) {
                        aup = (struct au1000_private *) dev->priv;
                        unregister_netdev(dev);
-                       if (aup->mii)
-                               kfree(aup->mii);
+                       kfree(aup->mii);
                        for (j = 0; j < NUM_RX_DMA; j++) {
                                if (aup->rx_db_inuse[j])
                                        ReleaseDB(aup, aup->rx_db_inuse[j]);
index 282ebd1..0ee3e27 100644 (file)
@@ -19,6 +19,7 @@
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/version.h>
+#include <linux/dma-mapping.h>
 
 #include <asm/uaccess.h>
 #include <asm/io.h>
@@ -1130,14 +1131,10 @@ static void b44_init_rings(struct b44 *bp)
  */
 static void b44_free_consistent(struct b44 *bp)
 {
-       if (bp->rx_buffers) {
-               kfree(bp->rx_buffers);
-               bp->rx_buffers = NULL;
-       }
-       if (bp->tx_buffers) {
-               kfree(bp->tx_buffers);
-               bp->tx_buffers = NULL;
-       }
+       kfree(bp->rx_buffers);
+       bp->rx_buffers = NULL;
+       kfree(bp->tx_buffers);
+       bp->tx_buffers = NULL;
        if (bp->rx_ring) {
                if (bp->flags & B44_FLAG_RX_RING_HACK) {
                        dma_unmap_single(&bp->pdev->dev, bp->rx_ring_dma,
@@ -1619,14 +1616,14 @@ static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 
        cmd->advertising = 0;
        if (bp->flags & B44_FLAG_ADV_10HALF)
-               cmd->advertising |= ADVERTISE_10HALF;
+               cmd->advertising |= ADVERTISED_10baseT_Half;
        if (bp->flags & B44_FLAG_ADV_10FULL)
-               cmd->advertising |= ADVERTISE_10FULL;
+               cmd->advertising |= ADVERTISED_10baseT_Full;
        if (bp->flags & B44_FLAG_ADV_100HALF)
-               cmd->advertising |= ADVERTISE_100HALF;
+               cmd->advertising |= ADVERTISED_100baseT_Half;
        if (bp->flags & B44_FLAG_ADV_100FULL)
-               cmd->advertising |= ADVERTISE_100FULL;
-       cmd->advertising |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
+               cmd->advertising |= ADVERTISED_100baseT_Full;
+       cmd->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
        cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
                SPEED_100 : SPEED_10;
        cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
@@ -2044,6 +2041,8 @@ static int b44_suspend(struct pci_dev *pdev, pm_message_t state)
        b44_free_rings(bp);
 
        spin_unlock_irq(&bp->lock);
+
+       free_irq(dev->irq, dev);
        pci_disable_device(pdev);
        return 0;
 }
@@ -2060,6 +2059,9 @@ static int b44_resume(struct pci_dev *pdev)
        if (!netif_running(dev))
                return 0;
 
+       if (request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev))
+               printk(KERN_ERR PFX "%s: request_irq failed\n", dev->name);
+
        spin_lock_irq(&bp->lock);
 
        b44_init_rings(bp);
index 60dba4a..73f2fcf 100644 (file)
@@ -1689,10 +1689,8 @@ static void __exit bmac_exit(void)
 {
        macio_unregister_driver(&bmac_driver);
 
-       if (bmac_emergency_rxbuf != NULL) {
-               kfree(bmac_emergency_rxbuf);
-               bmac_emergency_rxbuf = NULL;
-       }
+       kfree(bmac_emergency_rxbuf);
+       bmac_emergency_rxbuf = NULL;
 }
 
 MODULE_AUTHOR("Randy Gobbel/Paul Mackerras");
index 3a2ace0..11d2523 100644 (file)
@@ -314,20 +314,16 @@ bnx2_free_mem(struct bnx2 *bp)
                                    bp->tx_desc_ring, bp->tx_desc_mapping);
                bp->tx_desc_ring = NULL;
        }
-       if (bp->tx_buf_ring) {
-               kfree(bp->tx_buf_ring);
-               bp->tx_buf_ring = NULL;
-       }
+       kfree(bp->tx_buf_ring);
+       bp->tx_buf_ring = NULL;
        if (bp->rx_desc_ring) {
                pci_free_consistent(bp->pdev,
                                    sizeof(struct rx_bd) * RX_DESC_CNT,
                                    bp->rx_desc_ring, bp->rx_desc_mapping);
                bp->rx_desc_ring = NULL;
        }
-       if (bp->rx_buf_ring) {
-               kfree(bp->rx_buf_ring);
-               bp->rx_buf_ring = NULL;
-       }
+       kfree(bp->rx_buf_ring);
+       bp->rx_buf_ring = NULL;
 }
 
 static int
index 6b9acc7..9c7feae 100644 (file)
@@ -965,11 +965,8 @@ e1000_free_desc_rings(struct e1000_adapter *adapter)
        if(rxdr->desc)
                pci_free_consistent(pdev, rxdr->size, rxdr->desc, rxdr->dma);
 
-       if(txdr->buffer_info)
-               kfree(txdr->buffer_info);
-       if(rxdr->buffer_info)
-               kfree(rxdr->buffer_info);
-
+       kfree(txdr->buffer_info);
+       kfree(rxdr->buffer_info);
        return;
 }
 
index 6b72f6a..efbbda7 100644 (file)
@@ -191,8 +191,8 @@ static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
 static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
 static void e1000_restore_vlan(struct e1000_adapter *adapter);
 
-static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
 #ifdef CONFIG_PM
+static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
 static int e1000_resume(struct pci_dev *pdev);
 #endif
 
@@ -1149,7 +1149,8 @@ e1000_setup_tx_resources(struct e1000_adapter *adapter,
        int size;
 
        size = sizeof(struct e1000_buffer) * txdr->count;
-       txdr->buffer_info = vmalloc(size);
+
+       txdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
        if(!txdr->buffer_info) {
                DPRINTK(PROBE, ERR,
                "Unable to allocate memory for the transmit descriptor ring\n");
@@ -1366,7 +1367,7 @@ e1000_setup_rx_resources(struct e1000_adapter *adapter,
        int size, desc_len;
 
        size = sizeof(struct e1000_buffer) * rxdr->count;
-       rxdr->buffer_info = vmalloc(size);
+       rxdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
        if (!rxdr->buffer_info) {
                DPRINTK(PROBE, ERR,
                "Unable to allocate memory for the receive descriptor ring\n");
@@ -4193,6 +4194,7 @@ e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
        return 0;
 }
 
+#ifdef CONFIG_PM
 static int
 e1000_suspend(struct pci_dev *pdev, pm_message_t state)
 {
@@ -4289,7 +4291,6 @@ e1000_suspend(struct pci_dev *pdev, pm_message_t state)
        return 0;
 }
 
-#ifdef CONFIG_PM
 static int
 e1000_resume(struct pci_dev *pdev)
 {
index dcb3028..1ce2c67 100644 (file)
@@ -1797,10 +1797,9 @@ MODULE_AUTHOR("Pascal Dupuis and others");
 MODULE_DESCRIPTION("Intel i82595 ISA EtherExpressPro10/10+ driver");
 MODULE_LICENSE("GPL");
 
-static int num_params;
-module_param_array(io, int, &num_params, 0);
-module_param_array(irq, int, &num_params, 0);
-module_param_array(mem, int, &num_params, 0);
+module_param_array(io, int, NULL, 0);
+module_param_array(irq, int, NULL, 0);
+module_param_array(mem, int, NULL, 0);
 module_param(autodetect, int, 0);
 MODULE_PARM_DESC(io, "EtherExpress Pro/10 I/O base addres(es)");
 MODULE_PARM_DESC(irq, "EtherExpress Pro/10 IRQ number(s)");
diff --git a/drivers/net/fs_enet/Kconfig b/drivers/net/fs_enet/Kconfig
new file mode 100644 (file)
index 0000000..6aaee67
--- /dev/null
@@ -0,0 +1,20 @@
+config FS_ENET
+       tristate "Freescale Ethernet Driver"
+       depends on NET_ETHERNET && (CPM1 || CPM2)
+       select MII
+
+config FS_ENET_HAS_SCC
+       bool "Chip has an SCC usable for ethernet"
+       depends on FS_ENET && (CPM1 || CPM2)
+       default y
+
+config FS_ENET_HAS_FCC
+       bool "Chip has an FCC usable for ethernet"
+       depends on FS_ENET && CPM2
+       default y
+
+config FS_ENET_HAS_FEC
+       bool "Chip has an FEC usable for ethernet"
+       depends on FS_ENET && CPM1
+       default y
+
diff --git a/drivers/net/fs_enet/Makefile b/drivers/net/fs_enet/Makefile
new file mode 100644 (file)
index 0000000..d6dd3f2
--- /dev/null
@@ -0,0 +1,10 @@
+#
+# Makefile for the Freescale Ethernet controllers
+#
+
+obj-$(CONFIG_FS_ENET) += fs_enet.o
+
+obj-$(CONFIG_8xx) += mac-fec.o mac-scc.o
+obj-$(CONFIG_8260) += mac-fcc.o
+
+fs_enet-objs := fs_enet-main.o fs_enet-mii.o mii-bitbang.o mii-fixed.o
diff --git a/drivers/net/fs_enet/fs_enet-main.c b/drivers/net/fs_enet/fs_enet-main.c
new file mode 100644 (file)
index 0000000..44fac73
--- /dev/null
@@ -0,0 +1,1226 @@
+/*
+ * Combined Ethernet driver for Motorola MPC8xx and MPC82xx.
+ *
+ * Copyright (c) 2003 Intracom S.A. 
+ *  by Pantelis Antoniou <panto@intracom.gr>
+ * 
+ * 2005 (c) MontaVista Software, Inc. 
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * Heavily based on original FEC driver by Dan Malek <dan@embeddededge.com>
+ * and modifications by Joakim Tjernlund <joakim.tjernlund@lumentis.se>
+ *
+ * This file is licensed under the terms of the GNU General Public License 
+ * version 2. This program is licensed "as is" without any warranty of any 
+ * kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <linux/ptrace.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/spinlock.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/bitops.h>
+#include <linux/fs.h>
+
+#include <linux/vmalloc.h>
+#include <asm/pgtable.h>
+
+#include <asm/pgtable.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+
+#include "fs_enet.h"
+
+/*************************************************/
+
+static char version[] __devinitdata =
+    DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")" "\n";
+
+MODULE_AUTHOR("Pantelis Antoniou <panto@intracom.gr>");
+MODULE_DESCRIPTION("Freescale Ethernet Driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_MODULE_VERSION);
+
+MODULE_PARM(fs_enet_debug, "i");
+MODULE_PARM_DESC(fs_enet_debug,
+                "Freescale bitmapped debugging message enable value");
+
+int fs_enet_debug = -1;                /* -1 == use FS_ENET_DEF_MSG_ENABLE as value */
+
+static void fs_set_multicast_list(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+
+       (*fep->ops->set_multicast_list)(dev);
+}
+
+/* NAPI receive function */
+static int fs_enet_rx_napi(struct net_device *dev, int *budget)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       const struct fs_platform_info *fpi = fep->fpi;
+       cbd_t *bdp;
+       struct sk_buff *skb, *skbn, *skbt;
+       int received = 0;
+       u16 pkt_len, sc;
+       int curidx;
+       int rx_work_limit = 0;  /* pacify gcc */
+
+       rx_work_limit = min(dev->quota, *budget);
+
+       if (!netif_running(dev))
+               return 0;
+
+       /*
+        * First, grab all of the stats for the incoming packet.
+        * These get messed up if we get called due to a busy condition.
+        */
+       bdp = fep->cur_rx;
+
+       /* clear RX status bits for napi*/
+       (*fep->ops->napi_clear_rx_event)(dev);
+
+       while (((sc = CBDR_SC(bdp)) & BD_ENET_RX_EMPTY) == 0) {
+
+               curidx = bdp - fep->rx_bd_base;
+
+               /*
+                * Since we have allocated space to hold a complete frame,
+                * the last indicator should be set.
+                */
+               if ((sc & BD_ENET_RX_LAST) == 0)
+                       printk(KERN_WARNING DRV_MODULE_NAME
+                              ": %s rcv is not +last\n",
+                              dev->name);
+
+               /*
+                * Check for errors. 
+                */
+               if (sc & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_CL |
+                         BD_ENET_RX_NO | BD_ENET_RX_CR | BD_ENET_RX_OV)) {
+                       fep->stats.rx_errors++;
+                       /* Frame too long or too short. */
+                       if (sc & (BD_ENET_RX_LG | BD_ENET_RX_SH))
+                               fep->stats.rx_length_errors++;
+                       /* Frame alignment */
+                       if (sc & (BD_ENET_RX_NO | BD_ENET_RX_CL))
+                               fep->stats.rx_frame_errors++;
+                       /* CRC Error */
+                       if (sc & BD_ENET_RX_CR)
+                               fep->stats.rx_crc_errors++;
+                       /* FIFO overrun */
+                       if (sc & BD_ENET_RX_OV)
+                               fep->stats.rx_crc_errors++;
+
+                       skb = fep->rx_skbuff[curidx];
+
+                       dma_unmap_single(fep->dev, skb->data,
+                               L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
+                               DMA_FROM_DEVICE);
+
+                       skbn = skb;
+
+               } else {
+
+                       /* napi, got packet but no quota */
+                       if (--rx_work_limit < 0)
+                               break;
+
+                       skb = fep->rx_skbuff[curidx];
+
+                       dma_unmap_single(fep->dev, skb->data,
+                               L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
+                               DMA_FROM_DEVICE);
+
+                       /*
+                        * Process the incoming frame.
+                        */
+                       fep->stats.rx_packets++;
+                       pkt_len = CBDR_DATLEN(bdp) - 4; /* remove CRC */
+                       fep->stats.rx_bytes += pkt_len + 4;
+
+                       if (pkt_len <= fpi->rx_copybreak) {
+                               /* +2 to make IP header L1 cache aligned */
+                               skbn = dev_alloc_skb(pkt_len + 2);
+                               if (skbn != NULL) {
+                                       skb_reserve(skbn, 2);   /* align IP header */
+                                       memcpy(skbn->data, skb->data, pkt_len);
+                                       /* swap */
+                                       skbt = skb;
+                                       skb = skbn;
+                                       skbn = skbt;
+                               }
+                       } else
+                               skbn = dev_alloc_skb(ENET_RX_FRSIZE);
+
+                       if (skbn != NULL) {
+                               skb->dev = dev;
+                               skb_put(skb, pkt_len);  /* Make room */
+                               skb->protocol = eth_type_trans(skb, dev);
+                               received++;
+                               netif_receive_skb(skb);
+                       } else {
+                               printk(KERN_WARNING DRV_MODULE_NAME
+                                      ": %s Memory squeeze, dropping packet.\n",
+                                      dev->name);
+                               fep->stats.rx_dropped++;
+                               skbn = skb;
+                       }
+               }
+
+               fep->rx_skbuff[curidx] = skbn;
+               CBDW_BUFADDR(bdp, dma_map_single(fep->dev, skbn->data,
+                            L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
+                            DMA_FROM_DEVICE));
+               CBDW_DATLEN(bdp, 0);
+               CBDW_SC(bdp, (sc & ~BD_ENET_RX_STATS) | BD_ENET_RX_EMPTY);
+
+               /*
+                * Update BD pointer to next entry. 
+                */
+               if ((sc & BD_ENET_RX_WRAP) == 0)
+                       bdp++;
+               else
+                       bdp = fep->rx_bd_base;
+
+               (*fep->ops->rx_bd_done)(dev);
+       }
+
+       fep->cur_rx = bdp;
+
+       dev->quota -= received;
+       *budget -= received;
+
+       if (rx_work_limit < 0)
+               return 1;       /* not done */
+
+       /* done */
+       netif_rx_complete(dev);
+
+       (*fep->ops->napi_enable_rx)(dev);
+
+       return 0;
+}
+
+/* non NAPI receive function */
+static int fs_enet_rx_non_napi(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       const struct fs_platform_info *fpi = fep->fpi;
+       cbd_t *bdp;
+       struct sk_buff *skb, *skbn, *skbt;
+       int received = 0;
+       u16 pkt_len, sc;
+       int curidx;
+       /*
+        * First, grab all of the stats for the incoming packet.
+        * These get messed up if we get called due to a busy condition.
+        */
+       bdp = fep->cur_rx;
+
+       while (((sc = CBDR_SC(bdp)) & BD_ENET_RX_EMPTY) == 0) {
+
+               curidx = bdp - fep->rx_bd_base;
+
+               /*
+                * Since we have allocated space to hold a complete frame,
+                * the last indicator should be set.
+                */
+               if ((sc & BD_ENET_RX_LAST) == 0)
+                       printk(KERN_WARNING DRV_MODULE_NAME
+                              ": %s rcv is not +last\n",
+                              dev->name);
+
+               /*
+                * Check for errors. 
+                */
+               if (sc & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_CL |
+                         BD_ENET_RX_NO | BD_ENET_RX_CR | BD_ENET_RX_OV)) {
+                       fep->stats.rx_errors++;
+                       /* Frame too long or too short. */
+                       if (sc & (BD_ENET_RX_LG | BD_ENET_RX_SH))
+                               fep->stats.rx_length_errors++;
+                       /* Frame alignment */
+                       if (sc & (BD_ENET_RX_NO | BD_ENET_RX_CL))
+                               fep->stats.rx_frame_errors++;
+                       /* CRC Error */
+                       if (sc & BD_ENET_RX_CR)
+                               fep->stats.rx_crc_errors++;
+                       /* FIFO overrun */
+                       if (sc & BD_ENET_RX_OV)
+                               fep->stats.rx_crc_errors++;
+
+                       skb = fep->rx_skbuff[curidx];
+
+                       dma_unmap_single(fep->dev, skb->data,
+                               L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
+                               DMA_FROM_DEVICE);
+
+                       skbn = skb;
+
+               } else {
+
+                       skb = fep->rx_skbuff[curidx];
+
+                       dma_unmap_single(fep->dev, skb->data,
+                               L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
+                               DMA_FROM_DEVICE);
+
+                       /*
+                        * Process the incoming frame.
+                        */
+                       fep->stats.rx_packets++;
+                       pkt_len = CBDR_DATLEN(bdp) - 4; /* remove CRC */
+                       fep->stats.rx_bytes += pkt_len + 4;
+
+                       if (pkt_len <= fpi->rx_copybreak) {
+                               /* +2 to make IP header L1 cache aligned */
+                               skbn = dev_alloc_skb(pkt_len + 2);
+                               if (skbn != NULL) {
+                                       skb_reserve(skbn, 2);   /* align IP header */
+                                       memcpy(skbn->data, skb->data, pkt_len);
+                                       /* swap */
+                                       skbt = skb;
+                                       skb = skbn;
+                                       skbn = skbt;
+                               }
+                       } else
+                               skbn = dev_alloc_skb(ENET_RX_FRSIZE);
+
+                       if (skbn != NULL) {
+                               skb->dev = dev;
+                               skb_put(skb, pkt_len);  /* Make room */
+                               skb->protocol = eth_type_trans(skb, dev);
+                               received++;
+                               netif_rx(skb);
+                       } else {
+                               printk(KERN_WARNING DRV_MODULE_NAME
+                                      ": %s Memory squeeze, dropping packet.\n",
+                                      dev->name);
+                               fep->stats.rx_dropped++;
+                               skbn = skb;
+                       }
+               }
+
+               fep->rx_skbuff[curidx] = skbn;
+               CBDW_BUFADDR(bdp, dma_map_single(fep->dev, skbn->data,
+                            L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
+                            DMA_FROM_DEVICE));
+               CBDW_DATLEN(bdp, 0);
+               CBDW_SC(bdp, (sc & ~BD_ENET_RX_STATS) | BD_ENET_RX_EMPTY);
+
+               /*
+                * Update BD pointer to next entry. 
+                */
+               if ((sc & BD_ENET_RX_WRAP) == 0)
+                       bdp++;
+               else
+                       bdp = fep->rx_bd_base;
+
+               (*fep->ops->rx_bd_done)(dev);
+       }
+
+       fep->cur_rx = bdp;
+
+       return 0;
+}
+
+static void fs_enet_tx(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       cbd_t *bdp;
+       struct sk_buff *skb;
+       int dirtyidx, do_wake, do_restart;
+       u16 sc;
+
+       spin_lock(&fep->lock);
+       bdp = fep->dirty_tx;
+
+       do_wake = do_restart = 0;
+       while (((sc = CBDR_SC(bdp)) & BD_ENET_TX_READY) == 0) {
+
+               dirtyidx = bdp - fep->tx_bd_base;
+
+               if (fep->tx_free == fep->tx_ring)
+                       break;
+
+               skb = fep->tx_skbuff[dirtyidx];
+
+               /*
+                * Check for errors. 
+                */
+               if (sc & (BD_ENET_TX_HB | BD_ENET_TX_LC |
+                         BD_ENET_TX_RL | BD_ENET_TX_UN | BD_ENET_TX_CSL)) {
+
+                       if (sc & BD_ENET_TX_HB) /* No heartbeat */
+                               fep->stats.tx_heartbeat_errors++;
+                       if (sc & BD_ENET_TX_LC) /* Late collision */
+                               fep->stats.tx_window_errors++;
+                       if (sc & BD_ENET_TX_RL) /* Retrans limit */
+                               fep->stats.tx_aborted_errors++;
+                       if (sc & BD_ENET_TX_UN) /* Underrun */
+                               fep->stats.tx_fifo_errors++;
+                       if (sc & BD_ENET_TX_CSL)        /* Carrier lost */
+                               fep->stats.tx_carrier_errors++;
+
+                       if (sc & (BD_ENET_TX_LC | BD_ENET_TX_RL | BD_ENET_TX_UN)) {
+                               fep->stats.tx_errors++;
+                               do_restart = 1;
+                       }
+               } else
+                       fep->stats.tx_packets++;
+
+               if (sc & BD_ENET_TX_READY)
+                       printk(KERN_WARNING DRV_MODULE_NAME
+                              ": %s HEY! Enet xmit interrupt and TX_READY.\n",
+                              dev->name);
+
+               /*
+                * Deferred means some collisions occurred during transmit,
+                * but we eventually sent the packet OK.
+                */
+               if (sc & BD_ENET_TX_DEF)
+                       fep->stats.collisions++;
+
+               /* unmap */
+               dma_unmap_single(fep->dev, skb->data, skb->len, DMA_TO_DEVICE);
+
+               /*
+                * Free the sk buffer associated with this last transmit. 
+                */
+               dev_kfree_skb_irq(skb);
+               fep->tx_skbuff[dirtyidx] = NULL;
+
+               /*
+                * Update pointer to next buffer descriptor to be transmitted. 
+                */
+               if ((sc & BD_ENET_TX_WRAP) == 0)
+                       bdp++;
+               else
+                       bdp = fep->tx_bd_base;
+
+               /*
+                * Since we have freed up a buffer, the ring is no longer
+                * full.
+                */
+               if (!fep->tx_free++)
+                       do_wake = 1;
+       }
+
+       fep->dirty_tx = bdp;
+
+       if (do_restart)
+               (*fep->ops->tx_restart)(dev);
+
+       spin_unlock(&fep->lock);
+
+       if (do_wake)
+               netif_wake_queue(dev);
+}
+
+/*
+ * The interrupt handler.
+ * This is called from the MPC core interrupt.
+ */
+static irqreturn_t
+fs_enet_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+       struct net_device *dev = dev_id;
+       struct fs_enet_private *fep;
+       const struct fs_platform_info *fpi;
+       u32 int_events;
+       u32 int_clr_events;
+       int nr, napi_ok;
+       int handled;
+
+       fep = netdev_priv(dev);
+       fpi = fep->fpi;
+
+       nr = 0;
+       while ((int_events = (*fep->ops->get_int_events)(dev)) != 0) {
+
+               nr++;
+
+               int_clr_events = int_events;
+               if (fpi->use_napi)
+                       int_clr_events &= ~fep->ev_napi_rx;
+
+               (*fep->ops->clear_int_events)(dev, int_clr_events);
+
+               if (int_events & fep->ev_err)
+                       (*fep->ops->ev_error)(dev, int_events);
+
+               if (int_events & fep->ev_rx) {
+                       if (!fpi->use_napi)
+                               fs_enet_rx_non_napi(dev);
+                       else {
+                               napi_ok = netif_rx_schedule_prep(dev);
+
+                               (*fep->ops->napi_disable_rx)(dev);
+                               (*fep->ops->clear_int_events)(dev, fep->ev_napi_rx);
+
+                               /* NOTE: it is possible for FCCs in NAPI mode    */
+                               /* to submit a spurious interrupt while in poll  */
+                               if (napi_ok)
+                                       __netif_rx_schedule(dev);
+                       }
+               }
+
+               if (int_events & fep->ev_tx)
+                       fs_enet_tx(dev);
+       }
+
+       handled = nr > 0;
+       return IRQ_RETVAL(handled);
+}
+
+void fs_init_bds(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       cbd_t *bdp;
+       struct sk_buff *skb;
+       int i;
+
+       fs_cleanup_bds(dev);
+
+       fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
+       fep->tx_free = fep->tx_ring;
+       fep->cur_rx = fep->rx_bd_base;
+
+       /*
+        * Initialize the receive buffer descriptors. 
+        */
+       for (i = 0, bdp = fep->rx_bd_base; i < fep->rx_ring; i++, bdp++) {
+               skb = dev_alloc_skb(ENET_RX_FRSIZE);
+               if (skb == NULL) {
+                       printk(KERN_WARNING DRV_MODULE_NAME
+                              ": %s Memory squeeze, unable to allocate skb\n",
+                              dev->name);
+                       break;
+               }
+               fep->rx_skbuff[i] = skb;
+               skb->dev = dev;
+               CBDW_BUFADDR(bdp,
+                       dma_map_single(fep->dev, skb->data,
+                               L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
+                               DMA_FROM_DEVICE));
+               CBDW_DATLEN(bdp, 0);    /* zero */
+               CBDW_SC(bdp, BD_ENET_RX_EMPTY |
+                       ((i < fep->rx_ring - 1) ? 0 : BD_SC_WRAP));
+       }
+       /*
+        * if we failed, fillup remainder 
+        */
+       for (; i < fep->rx_ring; i++, bdp++) {
+               fep->rx_skbuff[i] = NULL;
+               CBDW_SC(bdp, (i < fep->rx_ring - 1) ? 0 : BD_SC_WRAP);
+       }
+
+       /*
+        * ...and the same for transmit.  
+        */
+       for (i = 0, bdp = fep->tx_bd_base; i < fep->tx_ring; i++, bdp++) {
+               fep->tx_skbuff[i] = NULL;
+               CBDW_BUFADDR(bdp, 0);
+               CBDW_DATLEN(bdp, 0);
+               CBDW_SC(bdp, (i < fep->tx_ring - 1) ? 0 : BD_SC_WRAP);
+       }
+}
+
+void fs_cleanup_bds(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       struct sk_buff *skb;
+       int i;
+
+       /*
+        * Reset SKB transmit buffers.  
+        */
+       for (i = 0; i < fep->tx_ring; i++) {
+               if ((skb = fep->tx_skbuff[i]) == NULL)
+                       continue;
+
+               /* unmap */
+               dma_unmap_single(fep->dev, skb->data, skb->len, DMA_TO_DEVICE);
+
+               fep->tx_skbuff[i] = NULL;
+               dev_kfree_skb(skb);
+       }
+
+       /*
+        * Reset SKB receive buffers 
+        */
+       for (i = 0; i < fep->rx_ring; i++) {
+               if ((skb = fep->rx_skbuff[i]) == NULL)
+                       continue;
+
+               /* unmap */
+               dma_unmap_single(fep->dev, skb->data,
+                       L1_CACHE_ALIGN(PKT_MAXBUF_SIZE),
+                       DMA_FROM_DEVICE);
+
+               fep->rx_skbuff[i] = NULL;
+
+               dev_kfree_skb(skb);
+       }
+}
+
+/**********************************************************************************/
+
+static int fs_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       cbd_t *bdp;
+       int curidx;
+       u16 sc;
+       unsigned long flags;
+
+       spin_lock_irqsave(&fep->tx_lock, flags);
+
+       /*
+        * Fill in a Tx ring entry 
+        */
+       bdp = fep->cur_tx;
+
+       if (!fep->tx_free || (CBDR_SC(bdp) & BD_ENET_TX_READY)) {
+               netif_stop_queue(dev);
+               spin_unlock_irqrestore(&fep->tx_lock, flags);
+
+               /*
+                * Ooops.  All transmit buffers are full.  Bail out.
+                * This should not happen, since the tx queue should be stopped.
+                */
+               printk(KERN_WARNING DRV_MODULE_NAME
+                      ": %s tx queue full!.\n", dev->name);
+               return NETDEV_TX_BUSY;
+       }
+
+       curidx = bdp - fep->tx_bd_base;
+       /*
+        * Clear all of the status flags. 
+        */
+       CBDC_SC(bdp, BD_ENET_TX_STATS);
+
+       /*
+        * Save skb pointer. 
+        */
+       fep->tx_skbuff[curidx] = skb;
+
+       fep->stats.tx_bytes += skb->len;
+
+       /*
+        * Push the data cache so the CPM does not get stale memory data. 
+        */
+       CBDW_BUFADDR(bdp, dma_map_single(fep->dev,
+                               skb->data, skb->len, DMA_TO_DEVICE));
+       CBDW_DATLEN(bdp, skb->len);
+
+       dev->trans_start = jiffies;
+
+       /*
+        * If this was the last BD in the ring, start at the beginning again. 
+        */
+       if ((CBDR_SC(bdp) & BD_ENET_TX_WRAP) == 0)
+               fep->cur_tx++;
+       else
+               fep->cur_tx = fep->tx_bd_base;
+
+       if (!--fep->tx_free)
+               netif_stop_queue(dev);
+
+       /* Trigger transmission start */
+       sc = BD_ENET_TX_READY | BD_ENET_TX_INTR |
+            BD_ENET_TX_LAST | BD_ENET_TX_TC;
+
+       /* note that while FEC does not have this bit
+        * it marks it as available for software use
+        * yay for hw reuse :) */
+       if (skb->len <= 60)
+               sc |= BD_ENET_TX_PAD;
+       CBDS_SC(bdp, sc);
+
+       (*fep->ops->tx_kickstart)(dev);
+
+       spin_unlock_irqrestore(&fep->tx_lock, flags);
+
+       return NETDEV_TX_OK;
+}
+
+static int fs_request_irq(struct net_device *dev, int irq, const char *name,
+               irqreturn_t (*irqf)(int irq, void *dev_id, struct pt_regs *regs))
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+
+       (*fep->ops->pre_request_irq)(dev, irq);
+       return request_irq(irq, irqf, SA_SHIRQ, name, dev);
+}
+
+static void fs_free_irq(struct net_device *dev, int irq)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+
+       free_irq(irq, dev);
+       (*fep->ops->post_free_irq)(dev, irq);
+}
+
+/**********************************************************************************/
+
+/* This interrupt occurs when the PHY detects a link change. */
+static irqreturn_t
+fs_mii_link_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+       struct net_device *dev = dev_id;
+       struct fs_enet_private *fep;
+       const struct fs_platform_info *fpi;
+
+       fep = netdev_priv(dev);
+       fpi = fep->fpi;
+
+       /*
+        * Acknowledge the interrupt if possible. If we have not
+        * found the PHY yet we can't process or acknowledge the
+        * interrupt now. Instead we ignore this interrupt for now,
+        * which we can do since it is edge triggered. It will be
+        * acknowledged later by fs_enet_open().
+        */
+       if (!fep->phy)
+               return IRQ_NONE;
+
+       fs_mii_ack_int(dev);
+       fs_mii_link_status_change_check(dev, 0);
+
+       return IRQ_HANDLED;
+}
+
+static void fs_timeout(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       unsigned long flags;
+       int wake = 0;
+
+       fep->stats.tx_errors++;
+
+       spin_lock_irqsave(&fep->lock, flags);
+
+       if (dev->flags & IFF_UP) {
+               (*fep->ops->stop)(dev);
+               (*fep->ops->restart)(dev);
+       }
+
+       wake = fep->tx_free && !(CBDR_SC(fep->cur_tx) & BD_ENET_TX_READY);
+       spin_unlock_irqrestore(&fep->lock, flags);
+
+       if (wake)
+               netif_wake_queue(dev);
+}
+
+static int fs_enet_open(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       const struct fs_platform_info *fpi = fep->fpi;
+       int r;
+
+       /* Install our interrupt handler. */
+       r = fs_request_irq(dev, fep->interrupt, "fs_enet-mac", fs_enet_interrupt);
+       if (r != 0) {
+               printk(KERN_ERR DRV_MODULE_NAME
+                      ": %s Could not allocate FEC IRQ!", dev->name);
+               return -EINVAL;
+       }
+
+       /* Install our phy interrupt handler */
+       if (fpi->phy_irq != -1) {
+
+               r = fs_request_irq(dev, fpi->phy_irq, "fs_enet-phy", fs_mii_link_interrupt);
+               if (r != 0) {
+                       printk(KERN_ERR DRV_MODULE_NAME
+                              ": %s Could not allocate PHY IRQ!", dev->name);
+                       fs_free_irq(dev, fep->interrupt);
+                       return -EINVAL;
+               }
+       }
+
+       fs_mii_startup(dev);
+       netif_carrier_off(dev);
+       fs_mii_link_status_change_check(dev, 1);
+
+       return 0;
+}
+
+static int fs_enet_close(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       const struct fs_platform_info *fpi = fep->fpi;
+       unsigned long flags;
+
+       netif_stop_queue(dev);
+       netif_carrier_off(dev);
+       fs_mii_shutdown(dev);
+
+       spin_lock_irqsave(&fep->lock, flags);
+       (*fep->ops->stop)(dev);
+       spin_unlock_irqrestore(&fep->lock, flags);
+
+       /* release any irqs */
+       if (fpi->phy_irq != -1)
+               fs_free_irq(dev, fpi->phy_irq);
+       fs_free_irq(dev, fep->interrupt);
+
+       return 0;
+}
+
+static struct net_device_stats *fs_enet_get_stats(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       return &fep->stats;
+}
+
+/*************************************************************************/
+
+static void fs_get_drvinfo(struct net_device *dev,
+                           struct ethtool_drvinfo *info)
+{
+       strcpy(info->driver, DRV_MODULE_NAME);
+       strcpy(info->version, DRV_MODULE_VERSION);
+}
+
+static int fs_get_regs_len(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+
+       return (*fep->ops->get_regs_len)(dev);
+}
+
+static void fs_get_regs(struct net_device *dev, struct ethtool_regs *regs,
+                        void *p)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       unsigned long flags;
+       int r, len;
+
+       len = regs->len;
+
+       spin_lock_irqsave(&fep->lock, flags);
+       r = (*fep->ops->get_regs)(dev, p, &len);
+       spin_unlock_irqrestore(&fep->lock, flags);
+
+       if (r == 0)
+               regs->version = 0;
+}
+
+static int fs_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       unsigned long flags;
+       int rc;
+
+       spin_lock_irqsave(&fep->lock, flags);
+       rc = mii_ethtool_gset(&fep->mii_if, cmd);
+       spin_unlock_irqrestore(&fep->lock, flags);
+
+       return rc;
+}
+
+static int fs_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       unsigned long flags;
+       int rc;
+
+       spin_lock_irqsave(&fep->lock, flags);
+       rc = mii_ethtool_sset(&fep->mii_if, cmd);
+       spin_unlock_irqrestore(&fep->lock, flags);
+
+       return rc;
+}
+
+static int fs_nway_reset(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       return mii_nway_restart(&fep->mii_if);
+}
+
+static u32 fs_get_msglevel(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       return fep->msg_enable;
+}
+
+static void fs_set_msglevel(struct net_device *dev, u32 value)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fep->msg_enable = value;
+}
+
+static struct ethtool_ops fs_ethtool_ops = {
+       .get_drvinfo = fs_get_drvinfo,
+       .get_regs_len = fs_get_regs_len,
+       .get_settings = fs_get_settings,
+       .set_settings = fs_set_settings,
+       .nway_reset = fs_nway_reset,
+       .get_link = ethtool_op_get_link,
+       .get_msglevel = fs_get_msglevel,
+       .set_msglevel = fs_set_msglevel,
+       .get_tx_csum = ethtool_op_get_tx_csum,
+       .set_tx_csum = ethtool_op_set_tx_csum,  /* local! */
+       .get_sg = ethtool_op_get_sg,
+       .set_sg = ethtool_op_set_sg,
+       .get_regs = fs_get_regs,
+};
+
+static int fs_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       struct mii_ioctl_data *mii = (struct mii_ioctl_data *)&rq->ifr_data;
+       unsigned long flags;
+       int rc;
+
+       if (!netif_running(dev))
+               return -EINVAL;
+
+       spin_lock_irqsave(&fep->lock, flags);
+       rc = generic_mii_ioctl(&fep->mii_if, mii, cmd, NULL);
+       spin_unlock_irqrestore(&fep->lock, flags);
+       return rc;
+}
+
+extern int fs_mii_connect(struct net_device *dev);
+extern void fs_mii_disconnect(struct net_device *dev);
+
+static struct net_device *fs_init_instance(struct device *dev,
+               const struct fs_platform_info *fpi)
+{
+       struct net_device *ndev = NULL;
+       struct fs_enet_private *fep = NULL;
+       int privsize, i, r, err = 0, registered = 0;
+
+       /* guard */
+       if ((unsigned int)fpi->fs_no >= FS_MAX_INDEX)
+               return ERR_PTR(-EINVAL);
+
+       privsize = sizeof(*fep) + (sizeof(struct sk_buff **) *
+                           (fpi->rx_ring + fpi->tx_ring));
+
+       ndev = alloc_etherdev(privsize);
+       if (!ndev) {
+               err = -ENOMEM;
+               goto err;
+       }
+       SET_MODULE_OWNER(ndev);
+
+       fep = netdev_priv(ndev);
+       memset(fep, 0, privsize);       /* clear everything */
+
+       fep->dev = dev;
+       dev_set_drvdata(dev, ndev);
+       fep->fpi = fpi;
+       if (fpi->init_ioports)
+               fpi->init_ioports();
+
+#ifdef CONFIG_FS_ENET_HAS_FEC
+       if (fs_get_fec_index(fpi->fs_no) >= 0)
+               fep->ops = &fs_fec_ops;
+#endif
+
+#ifdef CONFIG_FS_ENET_HAS_SCC
+       if (fs_get_scc_index(fpi->fs_no) >=0 )
+               fep->ops = &fs_scc_ops;
+#endif
+
+#ifdef CONFIG_FS_ENET_HAS_FCC
+       if (fs_get_fcc_index(fpi->fs_no) >= 0)
+               fep->ops = &fs_fcc_ops;
+#endif
+
+       if (fep->ops == NULL) {
+               printk(KERN_ERR DRV_MODULE_NAME
+                      ": %s No matching ops found (%d).\n",
+                      ndev->name, fpi->fs_no);
+               err = -EINVAL;
+               goto err;
+       }
+
+       r = (*fep->ops->setup_data)(ndev);
+       if (r != 0) {
+               printk(KERN_ERR DRV_MODULE_NAME
+                      ": %s setup_data failed\n",
+                       ndev->name);
+               err = r;
+               goto err;
+       }
+
+       /* point rx_skbuff, tx_skbuff */
+       fep->rx_skbuff = (struct sk_buff **)&fep[1];
+       fep->tx_skbuff = fep->rx_skbuff + fpi->rx_ring;
+
+       /* init locks */
+       spin_lock_init(&fep->lock);
+       spin_lock_init(&fep->tx_lock);
+
+       /*
+        * Set the Ethernet address. 
+        */
+       for (i = 0; i < 6; i++)
+               ndev->dev_addr[i] = fpi->macaddr[i];
+       
+       r = (*fep->ops->allocate_bd)(ndev);
+       
+       if (fep->ring_base == NULL) {
+               printk(KERN_ERR DRV_MODULE_NAME
+                      ": %s buffer descriptor alloc failed (%d).\n", ndev->name, r);
+               err = r;
+               goto err;
+       }
+
+       /*
+        * Set receive and transmit descriptor base.
+        */
+       fep->rx_bd_base = fep->ring_base;
+       fep->tx_bd_base = fep->rx_bd_base + fpi->rx_ring;
+
+       /* initialize ring size variables */
+       fep->tx_ring = fpi->tx_ring;
+       fep->rx_ring = fpi->rx_ring;
+
+       /*
+        * The FEC Ethernet specific entries in the device structure. 
+        */
+       ndev->open = fs_enet_open;
+       ndev->hard_start_xmit = fs_enet_start_xmit;
+       ndev->tx_timeout = fs_timeout;
+       ndev->watchdog_timeo = 2 * HZ;
+       ndev->stop = fs_enet_close;
+       ndev->get_stats = fs_enet_get_stats;
+       ndev->set_multicast_list = fs_set_multicast_list;
+       if (fpi->use_napi) {
+               ndev->poll = fs_enet_rx_napi;
+               ndev->weight = fpi->napi_weight;
+       }
+       ndev->ethtool_ops = &fs_ethtool_ops;
+       ndev->do_ioctl = fs_ioctl;
+
+       init_timer(&fep->phy_timer_list);
+
+       netif_carrier_off(ndev);
+
+       err = register_netdev(ndev);
+       if (err != 0) {
+               printk(KERN_ERR DRV_MODULE_NAME
+                      ": %s register_netdev failed.\n", ndev->name);
+               goto err;
+       }
+       registered = 1;
+
+       err = fs_mii_connect(ndev);
+       if (err != 0) {
+               printk(KERN_ERR DRV_MODULE_NAME
+                      ": %s fs_mii_connect failed.\n", ndev->name);
+               goto err;
+       }
+
+       return ndev;
+
+      err:
+       if (ndev != NULL) {
+
+               if (registered)
+                       unregister_netdev(ndev);
+
+               if (fep != NULL) {
+                       (*fep->ops->free_bd)(ndev);
+                       (*fep->ops->cleanup_data)(ndev);
+               }
+
+               free_netdev(ndev);
+       }
+
+       dev_set_drvdata(dev, NULL);
+
+       return ERR_PTR(err);
+}
+
+static int fs_cleanup_instance(struct net_device *ndev)
+{
+       struct fs_enet_private *fep;
+       const struct fs_platform_info *fpi;
+       struct device *dev;
+
+       if (ndev == NULL)
+               return -EINVAL;
+
+       fep = netdev_priv(ndev);
+       if (fep == NULL)
+               return -EINVAL;
+
+       fpi = fep->fpi;
+
+       fs_mii_disconnect(ndev);
+
+       unregister_netdev(ndev);
+
+       dma_free_coherent(fep->dev, (fpi->tx_ring + fpi->rx_ring) * sizeof(cbd_t),
+                         fep->ring_base, fep->ring_mem_addr);
+
+       /* reset it */
+       (*fep->ops->cleanup_data)(ndev);
+
+       dev = fep->dev;
+       if (dev != NULL) {
+               dev_set_drvdata(dev, NULL);
+               fep->dev = NULL;
+       }
+
+       free_netdev(ndev);
+
+       return 0;
+}
+
+/**************************************************************************************/
+
+/* handy pointer to the immap */
+void *fs_enet_immap = NULL;
+
+static int setup_immap(void)
+{
+       phys_addr_t paddr = 0;
+       unsigned long size = 0;
+
+#ifdef CONFIG_CPM1
+       paddr = IMAP_ADDR;
+       size = 0x10000; /* map 64K */
+#endif
+
+#ifdef CONFIG_CPM2
+       paddr = CPM_MAP_ADDR;
+       size = 0x40000; /* map 256 K */
+#endif
+       fs_enet_immap = ioremap(paddr, size);
+       if (fs_enet_immap == NULL)
+               return -EBADF;  /* XXX ahem; maybe just BUG_ON? */
+
+       return 0;
+}
+
+static void cleanup_immap(void)
+{
+       if (fs_enet_immap != NULL) {
+               iounmap(fs_enet_immap);
+               fs_enet_immap = NULL;
+       }
+}
+
+/**************************************************************************************/
+
+static int __devinit fs_enet_probe(struct device *dev)
+{
+       struct net_device *ndev;
+
+       /* no fixup - no device */
+       if (dev->platform_data == NULL) {
+               printk(KERN_INFO "fs_enet: "
+                               "probe called with no platform data; "
+                               "remove unused devices\n");
+               return -ENODEV;
+       }
+
+       ndev = fs_init_instance(dev, dev->platform_data);
+       if (IS_ERR(ndev))
+               return PTR_ERR(ndev);
+       return 0;
+}
+
+static int fs_enet_remove(struct device *dev)
+{
+       return fs_cleanup_instance(dev_get_drvdata(dev));
+}
+
+static struct device_driver fs_enet_fec_driver = {
+       .name           = "fsl-cpm-fec",
+       .bus            = &platform_bus_type,
+       .probe          = fs_enet_probe,
+       .remove         = fs_enet_remove,
+#ifdef CONFIG_PM
+/*     .suspend        = fs_enet_suspend,      TODO */
+/*     .resume         = fs_enet_resume,       TODO */
+#endif
+};
+
+static struct device_driver fs_enet_scc_driver = {
+       .name           = "fsl-cpm-scc",
+       .bus            = &platform_bus_type,
+       .probe          = fs_enet_probe,
+       .remove         = fs_enet_remove,
+#ifdef CONFIG_PM
+/*     .suspend        = fs_enet_suspend,      TODO */
+/*     .resume         = fs_enet_resume,       TODO */
+#endif
+};
+
+static struct device_driver fs_enet_fcc_driver = {
+       .name           = "fsl-cpm-fcc",
+       .bus            = &platform_bus_type,
+       .probe          = fs_enet_probe,
+       .remove         = fs_enet_remove,
+#ifdef CONFIG_PM
+/*     .suspend        = fs_enet_suspend,      TODO */
+/*     .resume         = fs_enet_resume,       TODO */
+#endif
+};
+
+static int __init fs_init(void)
+{
+       int r;
+
+       printk(KERN_INFO
+                       "%s", version);
+
+       r = setup_immap();
+       if (r != 0)
+               return r;
+       r = driver_register(&fs_enet_fec_driver);
+       if (r != 0)
+               goto err;
+
+       r = driver_register(&fs_enet_fcc_driver);
+       if (r != 0)
+               goto err;
+
+       r = driver_register(&fs_enet_scc_driver);
+       if (r != 0)
+               goto err;
+
+       return 0;
+err:
+       cleanup_immap();
+       return r;
+       
+}
+
+static void __exit fs_cleanup(void)
+{
+       driver_unregister(&fs_enet_fec_driver);
+       driver_unregister(&fs_enet_fcc_driver);
+       driver_unregister(&fs_enet_scc_driver);
+       cleanup_immap();
+}
+
+/**************************************************************************************/
+
+module_init(fs_init);
+module_exit(fs_cleanup);
diff --git a/drivers/net/fs_enet/fs_enet-mii.c b/drivers/net/fs_enet/fs_enet-mii.c
new file mode 100644 (file)
index 0000000..c677037
--- /dev/null
@@ -0,0 +1,507 @@
+/*
+ * Combined Ethernet driver for Motorola MPC8xx and MPC82xx.
+ *
+ * Copyright (c) 2003 Intracom S.A. 
+ *  by Pantelis Antoniou <panto@intracom.gr>
+ * 
+ * 2005 (c) MontaVista Software, Inc. 
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * Heavily based on original FEC driver by Dan Malek <dan@embeddededge.com>
+ * and modifications by Joakim Tjernlund <joakim.tjernlund@lumentis.se>
+ *
+ * This file is licensed under the terms of the GNU General Public License 
+ * version 2. This program is licensed "as is" without any warranty of any 
+ * kind, whether express or implied.
+ */
+
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <linux/ptrace.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/spinlock.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/bitops.h>
+
+#include <asm/pgtable.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+
+#include "fs_enet.h"
+
+/*************************************************/
+
+/*
+ * Generic PHY support.
+ * Should work for all PHYs, but link change is detected by polling
+ */
+
+static void generic_timer_callback(unsigned long data)
+{
+       struct net_device *dev = (struct net_device *)data;
+       struct fs_enet_private *fep = netdev_priv(dev);
+
+       fep->phy_timer_list.expires = jiffies + HZ / 2;
+
+       add_timer(&fep->phy_timer_list);
+
+       fs_mii_link_status_change_check(dev, 0);
+}
+
+static void generic_startup(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+
+       fep->phy_timer_list.expires = jiffies + HZ / 2; /* every 500ms */
+       fep->phy_timer_list.data = (unsigned long)dev;
+       fep->phy_timer_list.function = generic_timer_callback;
+       add_timer(&fep->phy_timer_list);
+}
+
+static void generic_shutdown(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+
+       del_timer_sync(&fep->phy_timer_list);
+}
+
+/* ------------------------------------------------------------------------- */
+/* The Davicom DM9161 is used on the NETTA board                            */
+
+/* register definitions */
+
+#define MII_DM9161_ANAR                4       /* Aux. Config Register         */
+#define MII_DM9161_ACR         16      /* Aux. Config Register         */
+#define MII_DM9161_ACSR                17      /* Aux. Config/Status Register  */
+#define MII_DM9161_10TCSR      18      /* 10BaseT Config/Status Reg.   */
+#define MII_DM9161_INTR                21      /* Interrupt Register           */
+#define MII_DM9161_RECR                22      /* Receive Error Counter Reg.   */
+#define MII_DM9161_DISCR       23      /* Disconnect Counter Register  */
+
+static void dm9161_startup(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+
+       fs_mii_write(dev, fep->mii_if.phy_id, MII_DM9161_INTR, 0x0000);
+       /* Start autonegotiation */
+       fs_mii_write(dev, fep->mii_if.phy_id, MII_BMCR, 0x1200);
+
+       set_current_state(TASK_UNINTERRUPTIBLE);
+       schedule_timeout(HZ*8);
+}
+
+static void dm9161_ack_int(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+
+       fs_mii_read(dev, fep->mii_if.phy_id, MII_DM9161_INTR);
+}
+
+static void dm9161_shutdown(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+
+       fs_mii_write(dev, fep->mii_if.phy_id, MII_DM9161_INTR, 0x0f00);
+}
+
+/**********************************************************************************/
+
+static const struct phy_info phy_info[] = {
+       {
+               .id = 0x00181b88,
+               .name = "DM9161",
+               .startup = dm9161_startup,
+               .ack_int = dm9161_ack_int,
+               .shutdown = dm9161_shutdown,
+       }, {
+               .id = 0,
+               .name = "GENERIC",
+               .startup = generic_startup,
+               .shutdown = generic_shutdown,
+       },
+};
+
+/**********************************************************************************/
+
+static int phy_id_detect(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       const struct fs_platform_info *fpi = fep->fpi;
+       struct fs_enet_mii_bus *bus = fep->mii_bus;
+       int i, r, start, end, phytype, physubtype;
+       const struct phy_info *phy;
+       int phy_hwid, phy_id;
+
+       phy_hwid = -1;
+       fep->phy = NULL;
+
+       /* auto-detect? */
+       if (fpi->phy_addr == -1) {
+               start = 1;
+               end = 32;
+       } else {                /* direct */
+               start = fpi->phy_addr;
+               end = start + 1;
+       }
+
+       for (phy_id = start; phy_id < end; phy_id++) {
+               /* skip already used phy addresses on this bus */ 
+               if (bus->usage_map & (1 << phy_id))
+                       continue;
+               r = fs_mii_read(dev, phy_id, MII_PHYSID1);
+               if (r == -1 || (phytype = (r & 0xffff)) == 0xffff)
+                       continue;
+               r = fs_mii_read(dev, phy_id, MII_PHYSID2);
+               if (r == -1 || (physubtype = (r & 0xffff)) == 0xffff)
+                       continue;
+               phy_hwid = (phytype << 16) | physubtype;
+               if (phy_hwid != -1)
+                       break;
+       }
+
+       if (phy_hwid == -1) {
+               printk(KERN_ERR DRV_MODULE_NAME
+                      ": %s No PHY detected! range=0x%02x-0x%02x\n",
+                       dev->name, start, end);
+               return -1;
+       }
+
+       for (i = 0, phy = phy_info; i < ARRAY_SIZE(phy_info); i++, phy++)
+               if (phy->id == (phy_hwid >> 4) || phy->id == 0)
+                       break;
+
+       if (i >= ARRAY_SIZE(phy_info)) {
+               printk(KERN_ERR DRV_MODULE_NAME
+                      ": %s PHY id 0x%08x is not supported!\n",
+                      dev->name, phy_hwid);
+               return -1;
+       }
+
+       fep->phy = phy;
+
+       /* mark this address as used */
+       bus->usage_map |= (1 << phy_id);
+
+       printk(KERN_INFO DRV_MODULE_NAME
+              ": %s Phy @ 0x%x, type %s (0x%08x)%s\n",
+              dev->name, phy_id, fep->phy->name, phy_hwid,
+              fpi->phy_addr == -1 ? " (auto-detected)" : "");
+
+       return phy_id;
+}
+
+void fs_mii_startup(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+
+       if (fep->phy->startup)
+               (*fep->phy->startup) (dev);
+}
+
+void fs_mii_shutdown(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+
+       if (fep->phy->shutdown)
+               (*fep->phy->shutdown) (dev);
+}
+
+void fs_mii_ack_int(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+
+       if (fep->phy->ack_int)
+               (*fep->phy->ack_int) (dev);
+}
+
+#define MII_LINK       0x0001
+#define MII_HALF       0x0002
+#define MII_FULL       0x0004
+#define MII_BASE4      0x0008
+#define MII_10M                0x0010
+#define MII_100M       0x0020
+#define MII_1G         0x0040
+#define MII_10G                0x0080
+
+/* return full mii info at one gulp, with a usable form */
+static unsigned int mii_full_status(struct mii_if_info *mii)
+{
+       unsigned int status;
+       int bmsr, adv, lpa, neg;
+       struct fs_enet_private* fep = netdev_priv(mii->dev);
+       
+       /* first, a dummy read, needed to latch some MII phys */
+       (void)mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR);
+       bmsr = mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR);
+
+       /* no link */
+       if ((bmsr & BMSR_LSTATUS) == 0)
+               return 0;
+
+       status = MII_LINK;
+       
+       /* Lets look what ANEG says if it's supported - otherwize we shall
+          take the right values from the platform info*/
+       if(!mii->force_media) {
+               /* autoneg not completed; don't bother */
+               if ((bmsr & BMSR_ANEGCOMPLETE) == 0)
+                       return 0;
+
+               adv = (*mii->mdio_read)(mii->dev, mii->phy_id, MII_ADVERTISE);
+               lpa = (*mii->mdio_read)(mii->dev, mii->phy_id, MII_LPA);
+
+               neg = lpa & adv;
+       } else {
+               neg = fep->fpi->bus_info->lpa;
+       }
+
+       if (neg & LPA_100FULL)
+               status |= MII_FULL | MII_100M;
+       else if (neg & LPA_100BASE4)
+               status |= MII_FULL | MII_BASE4 | MII_100M;
+       else if (neg & LPA_100HALF)
+               status |= MII_HALF | MII_100M;
+       else if (neg & LPA_10FULL)
+               status |= MII_FULL | MII_10M;
+       else
+               status |= MII_HALF | MII_10M;
+       
+       return status;
+}
+
+void fs_mii_link_status_change_check(struct net_device *dev, int init_media)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       struct mii_if_info *mii = &fep->mii_if;
+       unsigned int mii_status;
+       int ok_to_print, link, duplex, speed;
+       unsigned long flags;
+
+       ok_to_print = netif_msg_link(fep);
+
+       mii_status = mii_full_status(mii);
+
+       if (!init_media && mii_status == fep->last_mii_status)
+               return;
+
+       fep->last_mii_status = mii_status;
+
+       link = !!(mii_status & MII_LINK);
+       duplex = !!(mii_status & MII_FULL);
+       speed = (mii_status & MII_100M) ? 100 : 10;
+
+       if (link == 0) {
+               netif_carrier_off(mii->dev);
+               netif_stop_queue(dev);
+               if (!init_media) {
+                       spin_lock_irqsave(&fep->lock, flags);
+                       (*fep->ops->stop)(dev);
+                       spin_unlock_irqrestore(&fep->lock, flags);
+               }
+
+               if (ok_to_print)
+                       printk(KERN_INFO "%s: link down\n", mii->dev->name);
+
+       } else {
+
+               mii->full_duplex = duplex;
+
+               netif_carrier_on(mii->dev);
+
+               spin_lock_irqsave(&fep->lock, flags);
+               fep->duplex = duplex;
+               fep->speed = speed;
+               (*fep->ops->restart)(dev);
+               spin_unlock_irqrestore(&fep->lock, flags);
+
+               netif_start_queue(dev);
+
+               if (ok_to_print)
+                       printk(KERN_INFO "%s: link up, %dMbps, %s-duplex\n",
+                              dev->name, speed, duplex ? "full" : "half");
+       }
+}
+
+/**********************************************************************************/
+
+int fs_mii_read(struct net_device *dev, int phy_id, int location)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       struct fs_enet_mii_bus *bus = fep->mii_bus;
+
+       unsigned long flags;
+       int ret;
+
+       spin_lock_irqsave(&bus->mii_lock, flags);
+       ret = (*bus->mii_read)(bus, phy_id, location);
+       spin_unlock_irqrestore(&bus->mii_lock, flags);
+
+       return ret;
+}
+
+void fs_mii_write(struct net_device *dev, int phy_id, int location, int value)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       struct fs_enet_mii_bus *bus = fep->mii_bus;
+       unsigned long flags;
+
+       spin_lock_irqsave(&bus->mii_lock, flags);
+       (*bus->mii_write)(bus, phy_id, location, value);
+       spin_unlock_irqrestore(&bus->mii_lock, flags);
+}
+
+/*****************************************************************************/
+
+/* list of all registered mii buses */
+static LIST_HEAD(fs_mii_bus_list);
+
+static struct fs_enet_mii_bus *lookup_bus(int method, int id)
+{
+       struct list_head *ptr;
+       struct fs_enet_mii_bus *bus;
+
+       list_for_each(ptr, &fs_mii_bus_list) {
+               bus = list_entry(ptr, struct fs_enet_mii_bus, list);
+               if (bus->bus_info->method == method &&
+                       bus->bus_info->id == id)
+                       return bus;
+       }
+       return NULL;
+}
+
+static struct fs_enet_mii_bus *create_bus(const struct fs_mii_bus_info *bi)
+{
+       struct fs_enet_mii_bus *bus;
+       int ret = 0;
+
+       bus = kmalloc(sizeof(*bus), GFP_KERNEL);
+       if (bus == NULL) {
+               ret = -ENOMEM;
+               goto err;
+       }
+       memset(bus, 0, sizeof(*bus));
+       spin_lock_init(&bus->mii_lock);
+       bus->bus_info = bi;
+       bus->refs = 0;
+       bus->usage_map = 0;
+
+       /* perform initialization */
+       switch (bi->method) {
+
+               case fsmii_fixed:
+                       ret = fs_mii_fixed_init(bus);
+                       if (ret != 0)
+                               goto err;
+                       break;
+
+               case fsmii_bitbang:
+                       ret = fs_mii_bitbang_init(bus);
+                       if (ret != 0)
+                               goto err;
+                       break;
+#ifdef CONFIG_FS_ENET_HAS_FEC
+               case fsmii_fec:
+                       ret = fs_mii_fec_init(bus);
+                       if (ret != 0)
+                               goto err;
+                       break;
+#endif
+               default:
+                       ret = -EINVAL;
+                       goto err;
+       }
+
+       list_add(&bus->list, &fs_mii_bus_list);
+
+       return bus;
+
+err:
+       if (bus)
+               kfree(bus);
+       return ERR_PTR(ret);
+}
+
+static void destroy_bus(struct fs_enet_mii_bus *bus)
+{
+       /* remove from bus list */
+       list_del(&bus->list);
+
+       /* nothing more needed */
+       kfree(bus);
+}
+
+int fs_mii_connect(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       const struct fs_platform_info *fpi = fep->fpi;
+       struct fs_enet_mii_bus *bus = NULL;
+
+       /* check method validity */
+       switch (fpi->bus_info->method) {
+               case fsmii_fixed:
+               case fsmii_bitbang:
+                       break;
+#ifdef CONFIG_FS_ENET_HAS_FEC
+               case fsmii_fec:
+                       break;
+#endif
+               default:
+                       printk(KERN_ERR DRV_MODULE_NAME
+                              ": %s Unknown MII bus method (%d)!\n",
+                              dev->name, fpi->bus_info->method);
+                       return -EINVAL; 
+       }
+
+       bus = lookup_bus(fpi->bus_info->method, fpi->bus_info->id);
+
+       /* if not found create new bus */
+       if (bus == NULL) {
+               bus = create_bus(fpi->bus_info);
+               if (IS_ERR(bus)) {
+                       printk(KERN_ERR DRV_MODULE_NAME
+                              ": %s MII bus creation failure!\n", dev->name);
+                       return PTR_ERR(bus);
+               }
+       }
+
+       bus->refs++;
+
+       fep->mii_bus = bus;
+
+       fep->mii_if.dev = dev;
+       fep->mii_if.phy_id_mask = 0x1f;
+       fep->mii_if.reg_num_mask = 0x1f;
+       fep->mii_if.mdio_read = fs_mii_read;
+       fep->mii_if.mdio_write = fs_mii_write;
+       fep->mii_if.force_media = fpi->bus_info->disable_aneg;
+       fep->mii_if.phy_id = phy_id_detect(dev);
+
+       return 0;
+}
+
+void fs_mii_disconnect(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       struct fs_enet_mii_bus *bus = NULL;
+
+       bus = fep->mii_bus;
+       fep->mii_bus = NULL;
+
+       if (--bus->refs <= 0)
+               destroy_bus(bus);
+}
diff --git a/drivers/net/fs_enet/fs_enet.h b/drivers/net/fs_enet/fs_enet.h
new file mode 100644 (file)
index 0000000..1105543
--- /dev/null
@@ -0,0 +1,245 @@
+#ifndef FS_ENET_H
+#define FS_ENET_H
+
+#include <linux/mii.h>
+#include <linux/netdevice.h>
+#include <linux/types.h>
+#include <linux/version.h>
+#include <linux/list.h>
+
+#include <linux/fs_enet_pd.h>
+
+#include <asm/dma-mapping.h>
+
+#ifdef CONFIG_CPM1
+#include <asm/commproc.h>
+#endif
+
+#ifdef CONFIG_CPM2
+#include <asm/cpm2.h>
+#endif
+
+/* hw driver ops */
+struct fs_ops {
+       int (*setup_data)(struct net_device *dev);
+       int (*allocate_bd)(struct net_device *dev);
+       void (*free_bd)(struct net_device *dev);
+       void (*cleanup_data)(struct net_device *dev);
+       void (*set_multicast_list)(struct net_device *dev);
+       void (*restart)(struct net_device *dev);
+       void (*stop)(struct net_device *dev);
+       void (*pre_request_irq)(struct net_device *dev, int irq);
+       void (*post_free_irq)(struct net_device *dev, int irq);
+       void (*napi_clear_rx_event)(struct net_device *dev);
+       void (*napi_enable_rx)(struct net_device *dev);
+       void (*napi_disable_rx)(struct net_device *dev);
+       void (*rx_bd_done)(struct net_device *dev);
+       void (*tx_kickstart)(struct net_device *dev);
+       u32 (*get_int_events)(struct net_device *dev);
+       void (*clear_int_events)(struct net_device *dev, u32 int_events);
+       void (*ev_error)(struct net_device *dev, u32 int_events);
+       int (*get_regs)(struct net_device *dev, void *p, int *sizep);
+       int (*get_regs_len)(struct net_device *dev);
+       void (*tx_restart)(struct net_device *dev);
+};
+
+struct phy_info {
+       unsigned int id;
+       const char *name;
+       void (*startup) (struct net_device * dev);
+       void (*shutdown) (struct net_device * dev);
+       void (*ack_int) (struct net_device * dev);
+};
+
+/* The FEC stores dest/src/type, data, and checksum for receive packets.
+ */
+#define MAX_MTU 1508           /* Allow fullsized pppoe packets over VLAN */
+#define MIN_MTU 46             /* this is data size */
+#define CRC_LEN 4
+
+#define PKT_MAXBUF_SIZE                (MAX_MTU+ETH_HLEN+CRC_LEN)
+#define PKT_MINBUF_SIZE                (MIN_MTU+ETH_HLEN+CRC_LEN)
+
+/* Must be a multiple of 32 (to cover both FEC & FCC) */
+#define PKT_MAXBLR_SIZE                ((PKT_MAXBUF_SIZE + 31) & ~31)
+/* This is needed so that invalidate_xxx wont invalidate too much */
+#define ENET_RX_FRSIZE         L1_CACHE_ALIGN(PKT_MAXBUF_SIZE)
+
+struct fs_enet_mii_bus {
+       struct list_head list;
+       spinlock_t mii_lock;
+       const struct fs_mii_bus_info *bus_info;
+       int refs;
+       u32 usage_map;
+
+       int (*mii_read)(struct fs_enet_mii_bus *bus,
+                       int phy_id, int location);
+
+       void (*mii_write)(struct fs_enet_mii_bus *bus,
+                       int phy_id, int location, int value);
+
+       union {
+               struct {
+                       unsigned int mii_speed;
+                       void *fecp;
+               } fec;
+
+               struct {
+                       /* note that the actual port size may */
+                       /* be different; cpm(s) handle it OK  */
+                       u8 mdio_msk;
+                       u8 *mdio_dir;
+                       u8 *mdio_dat;
+                       u8 mdc_msk;
+                       u8 *mdc_dir;
+                       u8 *mdc_dat;
+               } bitbang;
+
+               struct {
+                       u16 lpa;
+               } fixed;
+       };
+};
+
+int fs_mii_bitbang_init(struct fs_enet_mii_bus *bus);
+int fs_mii_fixed_init(struct fs_enet_mii_bus *bus);
+int fs_mii_fec_init(struct fs_enet_mii_bus *bus);
+
+struct fs_enet_private {
+       struct device *dev;     /* pointer back to the device (must be initialized first) */
+       spinlock_t lock;        /* during all ops except TX pckt processing */
+       spinlock_t tx_lock;     /* during fs_start_xmit and fs_tx         */
+       const struct fs_platform_info *fpi;
+       const struct fs_ops *ops;
+       int rx_ring, tx_ring;
+       dma_addr_t ring_mem_addr;
+       void *ring_base;
+       struct sk_buff **rx_skbuff;
+       struct sk_buff **tx_skbuff;
+       cbd_t *rx_bd_base;      /* Address of Rx and Tx buffers.    */
+       cbd_t *tx_bd_base;
+       cbd_t *dirty_tx;        /* ring entries to be free()ed.     */
+       cbd_t *cur_rx;
+       cbd_t *cur_tx;
+       int tx_free;
+       struct net_device_stats stats;
+       struct timer_list phy_timer_list;
+       const struct phy_info *phy;
+       u32 msg_enable;
+       struct mii_if_info mii_if;
+       unsigned int last_mii_status;
+       struct fs_enet_mii_bus *mii_bus;
+       int interrupt;
+
+       int duplex, speed;      /* current settings */
+
+       /* event masks */
+       u32 ev_napi_rx;         /* mask of NAPI rx events */
+       u32 ev_rx;              /* rx event mask          */
+       u32 ev_tx;              /* tx event mask          */
+       u32 ev_err;             /* error event mask       */
+
+       u16 bd_rx_empty;        /* mask of BD rx empty    */
+       u16 bd_rx_err;          /* mask of BD rx errors   */
+
+       union {
+               struct {
+                       int idx;                /* FEC1 = 0, FEC2 = 1  */
+                       void *fecp;             /* hw registers        */
+                       u32 hthi, htlo;         /* state for multicast */
+               } fec;
+
+               struct {
+                       int idx;                /* FCC1-3 = 0-2        */
+                       void *fccp;             /* hw registers        */
+                       void *ep;               /* parameter ram       */
+                       void *fcccp;            /* hw registers cont.  */
+                       void *mem;              /* FCC DPRAM */
+                       u32 gaddrh, gaddrl;     /* group address       */
+               } fcc;
+
+               struct {
+                       int idx;                /* FEC1 = 0, FEC2 = 1  */
+                       void *sccp;             /* hw registers        */
+                       void *ep;               /* parameter ram       */
+                       u32 hthi, htlo;         /* state for multicast */
+               } scc;
+
+       };
+};
+
+/***************************************************************************/
+
+int fs_mii_read(struct net_device *dev, int phy_id, int location);
+void fs_mii_write(struct net_device *dev, int phy_id, int location, int value);
+
+void fs_mii_startup(struct net_device *dev);
+void fs_mii_shutdown(struct net_device *dev);
+void fs_mii_ack_int(struct net_device *dev);
+
+void fs_mii_link_status_change_check(struct net_device *dev, int init_media);
+
+void fs_init_bds(struct net_device *dev);
+void fs_cleanup_bds(struct net_device *dev);
+
+/***************************************************************************/
+
+#define DRV_MODULE_NAME                "fs_enet"
+#define PFX DRV_MODULE_NAME    ": "
+#define DRV_MODULE_VERSION     "1.0"
+#define DRV_MODULE_RELDATE     "Aug 8, 2005"
+
+/***************************************************************************/
+
+int fs_enet_platform_init(void);
+void fs_enet_platform_cleanup(void);
+
+/***************************************************************************/
+
+/* buffer descriptor access macros */
+
+/* access macros */
+#if defined(CONFIG_CPM1)
+/* for a a CPM1 __raw_xxx's are sufficient */
+#define __cbd_out32(addr, x)   __raw_writel(x, addr)
+#define __cbd_out16(addr, x)   __raw_writew(x, addr)
+#define __cbd_in32(addr)       __raw_readl(addr)
+#define __cbd_in16(addr)       __raw_readw(addr)
+#else
+/* for others play it safe */
+#define __cbd_out32(addr, x)   out_be32(addr, x)
+#define __cbd_out16(addr, x)   out_be16(addr, x)
+#define __cbd_in32(addr)       in_be32(addr)
+#define __cbd_in16(addr)       in_be16(addr)
+#endif
+
+/* write */
+#define CBDW_SC(_cbd, _sc)             __cbd_out16(&(_cbd)->cbd_sc, (_sc))
+#define CBDW_DATLEN(_cbd, _datlen)     __cbd_out16(&(_cbd)->cbd_datlen, (_datlen))
+#define CBDW_BUFADDR(_cbd, _bufaddr)   __cbd_out32(&(_cbd)->cbd_bufaddr, (_bufaddr))
+
+/* read */
+#define CBDR_SC(_cbd)                  __cbd_in16(&(_cbd)->cbd_sc)
+#define CBDR_DATLEN(_cbd)              __cbd_in16(&(_cbd)->cbd_datlen)
+#define CBDR_BUFADDR(_cbd)             __cbd_in32(&(_cbd)->cbd_bufaddr)
+
+/* set bits */
+#define CBDS_SC(_cbd, _sc)             CBDW_SC(_cbd, CBDR_SC(_cbd) | (_sc))
+
+/* clear bits */
+#define CBDC_SC(_cbd, _sc)             CBDW_SC(_cbd, CBDR_SC(_cbd) & ~(_sc))
+
+/*******************************************************************/
+
+extern const struct fs_ops fs_fec_ops;
+extern const struct fs_ops fs_fcc_ops;
+extern const struct fs_ops fs_scc_ops;
+
+/*******************************************************************/
+
+/* handy pointer to the immap */
+extern void *fs_enet_immap;
+
+/*******************************************************************/
+
+#endif
diff --git a/drivers/net/fs_enet/mac-fcc.c b/drivers/net/fs_enet/mac-fcc.c
new file mode 100644 (file)
index 0000000..a940b96
--- /dev/null
@@ -0,0 +1,578 @@
+/*
+ * FCC driver for Motorola MPC82xx (PQ2).
+ *
+ * Copyright (c) 2003 Intracom S.A. 
+ *  by Pantelis Antoniou <panto@intracom.gr>
+ *
+ * 2005 (c) MontaVista Software, Inc. 
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License 
+ * version 2. This program is licensed "as is" without any warranty of any 
+ * kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <linux/ptrace.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/spinlock.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/bitops.h>
+#include <linux/fs.h>
+
+#include <asm/immap_cpm2.h>
+#include <asm/mpc8260.h>
+#include <asm/cpm2.h>
+
+#include <asm/pgtable.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+
+#include "fs_enet.h"
+
+/*************************************************/
+
+/* FCC access macros */
+
+#define __fcc_out32(addr, x)   out_be32((unsigned *)addr, x)
+#define __fcc_out16(addr, x)   out_be16((unsigned short *)addr, x)
+#define __fcc_out8(addr, x)    out_8((unsigned char *)addr, x)
+#define __fcc_in32(addr)       in_be32((unsigned *)addr)
+#define __fcc_in16(addr)       in_be16((unsigned short *)addr)
+#define __fcc_in8(addr)                in_8((unsigned char *)addr)
+
+/* parameter space */
+
+/* write, read, set bits, clear bits */
+#define W32(_p, _m, _v)        __fcc_out32(&(_p)->_m, (_v))
+#define R32(_p, _m)    __fcc_in32(&(_p)->_m)
+#define S32(_p, _m, _v)        W32(_p, _m, R32(_p, _m) | (_v))
+#define C32(_p, _m, _v)        W32(_p, _m, R32(_p, _m) & ~(_v))
+
+#define W16(_p, _m, _v)        __fcc_out16(&(_p)->_m, (_v))
+#define R16(_p, _m)    __fcc_in16(&(_p)->_m)
+#define S16(_p, _m, _v)        W16(_p, _m, R16(_p, _m) | (_v))
+#define C16(_p, _m, _v)        W16(_p, _m, R16(_p, _m) & ~(_v))
+
+#define W8(_p, _m, _v) __fcc_out8(&(_p)->_m, (_v))
+#define R8(_p, _m)     __fcc_in8(&(_p)->_m)
+#define S8(_p, _m, _v) W8(_p, _m, R8(_p, _m) | (_v))
+#define C8(_p, _m, _v) W8(_p, _m, R8(_p, _m) & ~(_v))
+
+/*************************************************/
+
+#define FCC_MAX_MULTICAST_ADDRS        64
+
+#define mk_mii_read(REG)       (0x60020000 | ((REG & 0x1f) << 18))
+#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
+#define mk_mii_end             0
+
+#define MAX_CR_CMD_LOOPS       10000
+
+static inline int fcc_cr_cmd(struct fs_enet_private *fep, u32 mcn, u32 op)
+{
+       const struct fs_platform_info *fpi = fep->fpi;
+
+       cpm2_map_t *immap = fs_enet_immap;
+       cpm_cpm2_t *cpmp = &immap->im_cpm;
+       u32 v;
+       int i;
+
+       /* Currently I don't know what feature call will look like. But 
+          I guess there'd be something like do_cpm_cmd() which will require page & sblock */
+       v = mk_cr_cmd(fpi->cp_page, fpi->cp_block, mcn, op);
+       W32(cpmp, cp_cpcr, v | CPM_CR_FLG);
+       for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
+               if ((R32(cpmp, cp_cpcr) & CPM_CR_FLG) == 0)
+                       break;
+
+       if (i >= MAX_CR_CMD_LOOPS) {
+               printk(KERN_ERR "%s(): Not able to issue CPM command\n",
+                      __FUNCTION__);
+               return 1;
+       }
+
+       return 0;
+}
+
+static int do_pd_setup(struct fs_enet_private *fep)
+{
+       struct platform_device *pdev = to_platform_device(fep->dev);
+       struct resource *r;
+
+       /* Fill out IRQ field */
+       fep->interrupt = platform_get_irq(pdev, 0);
+
+       /* Attach the memory for the FCC Parameter RAM */
+       r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_pram");
+       fep->fcc.ep = (void *)r->start;
+
+       if (fep->fcc.ep == NULL)
+               return -EINVAL;
+
+       r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_regs");
+       fep->fcc.fccp = (void *)r->start;
+
+       if (fep->fcc.fccp == NULL)
+               return -EINVAL;
+
+       fep->fcc.fcccp = (void *)fep->fpi->fcc_regs_c;
+
+       if (fep->fcc.fcccp == NULL)
+               return -EINVAL;
+
+       return 0;
+}
+
+#define FCC_NAPI_RX_EVENT_MSK  (FCC_ENET_RXF | FCC_ENET_RXB)
+#define FCC_RX_EVENT           (FCC_ENET_RXF)
+#define FCC_TX_EVENT           (FCC_ENET_TXB)
+#define FCC_ERR_EVENT_MSK      (FCC_ENET_TXE | FCC_ENET_BSY)
+
+static int setup_data(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       const struct fs_platform_info *fpi = fep->fpi;
+
+       fep->fcc.idx = fs_get_fcc_index(fpi->fs_no);
+       if ((unsigned int)fep->fcc.idx >= 3)    /* max 3 FCCs */
+               return -EINVAL;
+
+       fep->fcc.mem = (void *)fpi->mem_offset;
+
+       if (do_pd_setup(fep) != 0)
+               return -EINVAL;
+
+       fep->ev_napi_rx = FCC_NAPI_RX_EVENT_MSK;
+       fep->ev_rx = FCC_RX_EVENT;
+       fep->ev_tx = FCC_TX_EVENT;
+       fep->ev_err = FCC_ERR_EVENT_MSK;
+
+       return 0;
+}
+
+static int allocate_bd(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       const struct fs_platform_info *fpi = fep->fpi;
+
+       fep->ring_base = dma_alloc_coherent(fep->dev,
+                                           (fpi->tx_ring + fpi->rx_ring) *
+                                           sizeof(cbd_t), &fep->ring_mem_addr,
+                                           GFP_KERNEL);
+       if (fep->ring_base == NULL)
+               return -ENOMEM;
+
+       return 0;
+}
+
+static void free_bd(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       const struct fs_platform_info *fpi = fep->fpi;
+
+       if (fep->ring_base)
+               dma_free_coherent(fep->dev,
+                       (fpi->tx_ring + fpi->rx_ring) * sizeof(cbd_t),
+                       fep->ring_base, fep->ring_mem_addr);
+}
+
+static void cleanup_data(struct net_device *dev)
+{
+       /* nothing */
+}
+
+static void set_promiscuous_mode(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fcc_t *fccp = fep->fcc.fccp;
+
+       S32(fccp, fcc_fpsmr, FCC_PSMR_PRO);
+}
+
+static void set_multicast_start(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fcc_enet_t *ep = fep->fcc.ep;
+
+       W32(ep, fen_gaddrh, 0);
+       W32(ep, fen_gaddrl, 0);
+}
+
+static void set_multicast_one(struct net_device *dev, const u8 *mac)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fcc_enet_t *ep = fep->fcc.ep;
+       u16 taddrh, taddrm, taddrl;
+
+       taddrh = ((u16)mac[5] << 8) | mac[4];
+       taddrm = ((u16)mac[3] << 8) | mac[2];
+       taddrl = ((u16)mac[1] << 8) | mac[0];
+
+       W16(ep, fen_taddrh, taddrh);
+       W16(ep, fen_taddrm, taddrm);
+       W16(ep, fen_taddrl, taddrl);
+       fcc_cr_cmd(fep, 0x0C, CPM_CR_SET_GADDR);
+}
+
+static void set_multicast_finish(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fcc_t *fccp = fep->fcc.fccp;
+       fcc_enet_t *ep = fep->fcc.ep;
+
+       /* clear promiscuous always */
+       C32(fccp, fcc_fpsmr, FCC_PSMR_PRO);
+
+       /* if all multi or too many multicasts; just enable all */
+       if ((dev->flags & IFF_ALLMULTI) != 0 ||
+           dev->mc_count > FCC_MAX_MULTICAST_ADDRS) {
+
+               W32(ep, fen_gaddrh, 0xffffffff);
+               W32(ep, fen_gaddrl, 0xffffffff);
+       }
+
+       /* read back */
+       fep->fcc.gaddrh = R32(ep, fen_gaddrh);
+       fep->fcc.gaddrl = R32(ep, fen_gaddrl);
+}
+
+static void set_multicast_list(struct net_device *dev)
+{
+       struct dev_mc_list *pmc;
+
+       if ((dev->flags & IFF_PROMISC) == 0) {
+               set_multicast_start(dev);
+               for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
+                       set_multicast_one(dev, pmc->dmi_addr);
+               set_multicast_finish(dev);
+       } else
+               set_promiscuous_mode(dev);
+}
+
+static void restart(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       const struct fs_platform_info *fpi = fep->fpi;
+       fcc_t *fccp = fep->fcc.fccp;
+       fcc_c_t *fcccp = fep->fcc.fcccp;
+       fcc_enet_t *ep = fep->fcc.ep;
+       dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
+       u16 paddrh, paddrm, paddrl;
+       u16 mem_addr;
+       const unsigned char *mac;
+       int i;
+
+       C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
+
+       /* clear everything (slow & steady does it) */
+       for (i = 0; i < sizeof(*ep); i++)
+               __fcc_out8((char *)ep + i, 0);
+
+       /* get physical address */
+       rx_bd_base_phys = fep->ring_mem_addr;
+       tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
+
+       /* point to bds */
+       W32(ep, fen_genfcc.fcc_rbase, rx_bd_base_phys);
+       W32(ep, fen_genfcc.fcc_tbase, tx_bd_base_phys);
+
+       /* Set maximum bytes per receive buffer.
+        * It must be a multiple of 32.
+        */
+       W16(ep, fen_genfcc.fcc_mrblr, PKT_MAXBLR_SIZE);
+
+       W32(ep, fen_genfcc.fcc_rstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
+       W32(ep, fen_genfcc.fcc_tstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
+
+       /* Allocate space in the reserved FCC area of DPRAM for the
+        * internal buffers.  No one uses this space (yet), so we
+        * can do this.  Later, we will add resource management for
+        * this area.
+        */
+
+       mem_addr = (u32) fep->fcc.mem;  /* de-fixup dpram offset */
+
+       W16(ep, fen_genfcc.fcc_riptr, (mem_addr & 0xffff));
+       W16(ep, fen_genfcc.fcc_tiptr, ((mem_addr + 32) & 0xffff));
+       W16(ep, fen_padptr, mem_addr + 64);
+
+       /* fill with special symbol...  */
+       memset(fep->fcc.mem + fpi->dpram_offset + 64, 0x88, 32);
+
+       W32(ep, fen_genfcc.fcc_rbptr, 0);
+       W32(ep, fen_genfcc.fcc_tbptr, 0);
+       W32(ep, fen_genfcc.fcc_rcrc, 0);
+       W32(ep, fen_genfcc.fcc_tcrc, 0);
+       W16(ep, fen_genfcc.fcc_res1, 0);
+       W32(ep, fen_genfcc.fcc_res2, 0);
+
+       /* no CAM */
+       W32(ep, fen_camptr, 0);
+
+       /* Set CRC preset and mask */
+       W32(ep, fen_cmask, 0xdebb20e3);
+       W32(ep, fen_cpres, 0xffffffff);
+
+       W32(ep, fen_crcec, 0);          /* CRC Error counter       */
+       W32(ep, fen_alec, 0);           /* alignment error counter */
+       W32(ep, fen_disfc, 0);          /* discard frame counter   */
+       W16(ep, fen_retlim, 15);        /* Retry limit threshold   */
+       W16(ep, fen_pper, 0);           /* Normal persistence      */
+
+       /* set group address */
+       W32(ep, fen_gaddrh, fep->fcc.gaddrh);
+       W32(ep, fen_gaddrl, fep->fcc.gaddrh);
+
+       /* Clear hash filter tables */
+       W32(ep, fen_iaddrh, 0);
+       W32(ep, fen_iaddrl, 0);
+
+       /* Clear the Out-of-sequence TxBD  */
+       W16(ep, fen_tfcstat, 0);
+       W16(ep, fen_tfclen, 0);
+       W32(ep, fen_tfcptr, 0);
+
+       W16(ep, fen_mflr, PKT_MAXBUF_SIZE);     /* maximum frame length register */
+       W16(ep, fen_minflr, PKT_MINBUF_SIZE);   /* minimum frame length register */
+
+       /* set address */
+       mac = dev->dev_addr;
+       paddrh = ((u16)mac[5] << 8) | mac[4];
+       paddrm = ((u16)mac[3] << 8) | mac[2];
+       paddrl = ((u16)mac[1] << 8) | mac[0];
+
+       W16(ep, fen_paddrh, paddrh);
+       W16(ep, fen_paddrm, paddrm);
+       W16(ep, fen_paddrl, paddrl);
+
+       W16(ep, fen_taddrh, 0);
+       W16(ep, fen_taddrm, 0);
+       W16(ep, fen_taddrl, 0);
+
+       W16(ep, fen_maxd1, 1520);       /* maximum DMA1 length */
+       W16(ep, fen_maxd2, 1520);       /* maximum DMA2 length */
+
+       /* Clear stat counters, in case we ever enable RMON */
+       W32(ep, fen_octc, 0);
+       W32(ep, fen_colc, 0);
+       W32(ep, fen_broc, 0);
+       W32(ep, fen_mulc, 0);
+       W32(ep, fen_uspc, 0);
+       W32(ep, fen_frgc, 0);
+       W32(ep, fen_ospc, 0);
+       W32(ep, fen_jbrc, 0);
+       W32(ep, fen_p64c, 0);
+       W32(ep, fen_p65c, 0);
+       W32(ep, fen_p128c, 0);
+       W32(ep, fen_p256c, 0);
+       W32(ep, fen_p512c, 0);
+       W32(ep, fen_p1024c, 0);
+
+       W16(ep, fen_rfthr, 0);  /* Suggested by manual */
+       W16(ep, fen_rfcnt, 0);
+       W16(ep, fen_cftype, 0);
+
+       fs_init_bds(dev);
+
+       /* adjust to speed (for RMII mode) */
+       if (fpi->use_rmii) {
+               if (fep->speed == 100)
+                       C8(fcccp, fcc_gfemr, 0x20);
+               else
+                       S8(fcccp, fcc_gfemr, 0x20);
+       }
+
+       fcc_cr_cmd(fep, 0x0c, CPM_CR_INIT_TRX);
+
+       /* clear events */
+       W16(fccp, fcc_fcce, 0xffff);
+
+       /* Enable interrupts we wish to service */
+       W16(fccp, fcc_fccm, FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB);
+
+       /* Set GFMR to enable Ethernet operating mode */
+       W32(fccp, fcc_gfmr, FCC_GFMR_TCI | FCC_GFMR_MODE_ENET);
+
+       /* set sync/delimiters */
+       W16(fccp, fcc_fdsr, 0xd555);
+
+       W32(fccp, fcc_fpsmr, FCC_PSMR_ENCRC);
+
+       if (fpi->use_rmii)
+               S32(fccp, fcc_fpsmr, FCC_PSMR_RMII);
+
+       /* adjust to duplex mode */
+       if (fep->duplex)
+               S32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
+       else
+               C32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
+
+       S32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
+}
+
+static void stop(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fcc_t *fccp = fep->fcc.fccp;
+
+       /* stop ethernet */
+       C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
+
+       /* clear events */
+       W16(fccp, fcc_fcce, 0xffff);
+
+       /* clear interrupt mask */
+       W16(fccp, fcc_fccm, 0);
+
+       fs_cleanup_bds(dev);
+}
+
+static void pre_request_irq(struct net_device *dev, int irq)
+{
+       /* nothing */
+}
+
+static void post_free_irq(struct net_device *dev, int irq)
+{
+       /* nothing */
+}
+
+static void napi_clear_rx_event(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fcc_t *fccp = fep->fcc.fccp;
+
+       W16(fccp, fcc_fcce, FCC_NAPI_RX_EVENT_MSK);
+}
+
+static void napi_enable_rx(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fcc_t *fccp = fep->fcc.fccp;
+
+       S16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK);
+}
+
+static void napi_disable_rx(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fcc_t *fccp = fep->fcc.fccp;
+
+       C16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK);
+}
+
+static void rx_bd_done(struct net_device *dev)
+{
+       /* nothing */
+}
+
+static void tx_kickstart(struct net_device *dev)
+{
+       /* nothing */
+}
+
+static u32 get_int_events(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fcc_t *fccp = fep->fcc.fccp;
+
+       return (u32)R16(fccp, fcc_fcce);
+}
+
+static void clear_int_events(struct net_device *dev, u32 int_events)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fcc_t *fccp = fep->fcc.fccp;
+
+       W16(fccp, fcc_fcce, int_events & 0xffff);
+}
+
+static void ev_error(struct net_device *dev, u32 int_events)
+{
+       printk(KERN_WARNING DRV_MODULE_NAME
+              ": %s FS_ENET ERROR(s) 0x%x\n", dev->name, int_events);
+}
+
+int get_regs(struct net_device *dev, void *p, int *sizep)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+
+       if (*sizep < sizeof(fcc_t) + sizeof(fcc_c_t) + sizeof(fcc_enet_t))
+               return -EINVAL;
+
+       memcpy_fromio(p, fep->fcc.fccp, sizeof(fcc_t));
+       p = (char *)p + sizeof(fcc_t);
+
+       memcpy_fromio(p, fep->fcc.fcccp, sizeof(fcc_c_t));
+       p = (char *)p + sizeof(fcc_c_t);
+
+       memcpy_fromio(p, fep->fcc.ep, sizeof(fcc_enet_t));
+
+       return 0;
+}
+
+int get_regs_len(struct net_device *dev)
+{
+       return sizeof(fcc_t) + sizeof(fcc_c_t) + sizeof(fcc_enet_t);
+}
+
+/* Some transmit errors cause the transmitter to shut
+ * down.  We now issue a restart transmit.  Since the
+ * errors close the BD and update the pointers, the restart
+ * _should_ pick up without having to reset any of our
+ * pointers either.  Also, To workaround 8260 device erratum 
+ * CPM37, we must disable and then re-enable the transmitter
+ * following a Late Collision, Underrun, or Retry Limit error.
+ */
+void tx_restart(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fcc_t *fccp = fep->fcc.fccp;
+
+       C32(fccp, fcc_gfmr, FCC_GFMR_ENT);
+       udelay(10);
+       S32(fccp, fcc_gfmr, FCC_GFMR_ENT);
+
+       fcc_cr_cmd(fep, 0x0C, CPM_CR_RESTART_TX);
+}
+
+/*************************************************************************/
+
+const struct fs_ops fs_fcc_ops = {
+       .setup_data             = setup_data,
+       .cleanup_data           = cleanup_data,
+       .set_multicast_list     = set_multicast_list,
+       .restart                = restart,
+       .stop                   = stop,
+       .pre_request_irq        = pre_request_irq,
+       .post_free_irq          = post_free_irq,
+       .napi_clear_rx_event    = napi_clear_rx_event,
+       .napi_enable_rx         = napi_enable_rx,
+       .napi_disable_rx        = napi_disable_rx,
+       .rx_bd_done             = rx_bd_done,
+       .tx_kickstart           = tx_kickstart,
+       .get_int_events         = get_int_events,
+       .clear_int_events       = clear_int_events,
+       .ev_error               = ev_error,
+       .get_regs               = get_regs,
+       .get_regs_len           = get_regs_len,
+       .tx_restart             = tx_restart,
+       .allocate_bd            = allocate_bd,
+       .free_bd                = free_bd,
+};
diff --git a/drivers/net/fs_enet/mac-fec.c b/drivers/net/fs_enet/mac-fec.c
new file mode 100644 (file)
index 0000000..5ef4e84
--- /dev/null
@@ -0,0 +1,653 @@
+/*
+ * Freescale Ethernet controllers
+ *
+ * Copyright (c) 2005 Intracom S.A. 
+ *  by Pantelis Antoniou <panto@intracom.gr>
+ *
+ * 2005 (c) MontaVista Software, Inc. 
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License 
+ * version 2. This program is licensed "as is" without any warranty of any 
+ * kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <linux/ptrace.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/spinlock.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/bitops.h>
+#include <linux/fs.h>
+
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+
+#ifdef CONFIG_8xx
+#include <asm/8xx_immap.h>
+#include <asm/pgtable.h>
+#include <asm/mpc8xx.h>
+#include <asm/commproc.h>
+#endif
+
+#include "fs_enet.h"
+
+/*************************************************/
+
+#if defined(CONFIG_CPM1)
+/* for a CPM1 __raw_xxx's are sufficient */
+#define __fs_out32(addr, x)    __raw_writel(x, addr)
+#define __fs_out16(addr, x)    __raw_writew(x, addr)
+#define __fs_in32(addr)        __raw_readl(addr)
+#define __fs_in16(addr)        __raw_readw(addr)
+#else
+/* for others play it safe */
+#define __fs_out32(addr, x)    out_be32(addr, x)
+#define __fs_out16(addr, x)    out_be16(addr, x)
+#define __fs_in32(addr)        in_be32(addr)
+#define __fs_in16(addr)        in_be16(addr)
+#endif
+
+/* write */
+#define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v))
+
+/* read */
+#define FR(_fecp, _reg)        __fs_in32(&(_fecp)->fec_ ## _reg)
+
+/* set bits */
+#define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v))
+
+/* clear bits */
+#define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v))
+
+
+/* CRC polynomium used by the FEC for the multicast group filtering */
+#define FEC_CRC_POLY   0x04C11DB7
+
+#define FEC_MAX_MULTICAST_ADDRS        64
+
+/* Interrupt events/masks.
+*/
+#define FEC_ENET_HBERR 0x80000000U     /* Heartbeat error          */
+#define FEC_ENET_BABR  0x40000000U     /* Babbling receiver        */
+#define FEC_ENET_BABT  0x20000000U     /* Babbling transmitter     */
+#define FEC_ENET_GRA   0x10000000U     /* Graceful stop complete   */
+#define FEC_ENET_TXF   0x08000000U     /* Full frame transmitted   */
+#define FEC_ENET_TXB   0x04000000U     /* A buffer was transmitted */
+#define FEC_ENET_RXF   0x02000000U     /* Full frame received      */
+#define FEC_ENET_RXB   0x01000000U     /* A buffer was received    */
+#define FEC_ENET_MII   0x00800000U     /* MII interrupt            */
+#define FEC_ENET_EBERR 0x00400000U     /* SDMA bus error           */
+
+#define FEC_ECNTRL_PINMUX      0x00000004
+#define FEC_ECNTRL_ETHER_EN    0x00000002
+#define FEC_ECNTRL_RESET       0x00000001
+
+#define FEC_RCNTRL_BC_REJ      0x00000010
+#define FEC_RCNTRL_PROM                0x00000008
+#define FEC_RCNTRL_MII_MODE    0x00000004
+#define FEC_RCNTRL_DRT         0x00000002
+#define FEC_RCNTRL_LOOP                0x00000001
+
+#define FEC_TCNTRL_FDEN                0x00000004
+#define FEC_TCNTRL_HBC         0x00000002
+#define FEC_TCNTRL_GTS         0x00000001
+
+
+/* Make MII read/write commands for the FEC.
+*/
+#define mk_mii_read(REG)       (0x60020000 | ((REG & 0x1f) << 18))
+#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
+#define mk_mii_end             0
+
+#define FEC_MII_LOOPS  10000
+
+/*
+ * Delay to wait for FEC reset command to complete (in us) 
+ */
+#define FEC_RESET_DELAY                50
+
+static int whack_reset(fec_t * fecp)
+{
+       int i;
+
+       FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
+       for (i = 0; i < FEC_RESET_DELAY; i++) {
+               if ((FR(fecp, ecntrl) & FEC_ECNTRL_RESET) == 0)
+                       return 0;       /* OK */
+               udelay(1);
+       }
+
+       return -1;
+}
+
+static int do_pd_setup(struct fs_enet_private *fep)
+{
+       struct platform_device *pdev = to_platform_device(fep->dev); 
+       struct resource *r;
+       
+       /* Fill out IRQ field */
+       fep->interrupt = platform_get_irq_byname(pdev,"interrupt");
+       
+       r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
+       fep->fec.fecp =(void*)r->start;
+
+       if(fep->fec.fecp == NULL)
+               return -EINVAL;
+
+       return 0;
+       
+}
+
+#define FEC_NAPI_RX_EVENT_MSK  (FEC_ENET_RXF | FEC_ENET_RXB)
+#define FEC_RX_EVENT           (FEC_ENET_RXF)
+#define FEC_TX_EVENT           (FEC_ENET_TXF)
+#define FEC_ERR_EVENT_MSK      (FEC_ENET_HBERR | FEC_ENET_BABR | \
+                                FEC_ENET_BABT | FEC_ENET_EBERR)
+
+static int setup_data(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+
+       if (do_pd_setup(fep) != 0)
+               return -EINVAL;
+
+       fep->fec.hthi = 0;
+       fep->fec.htlo = 0;
+
+       fep->ev_napi_rx = FEC_NAPI_RX_EVENT_MSK;
+       fep->ev_rx = FEC_RX_EVENT;
+       fep->ev_tx = FEC_TX_EVENT;
+       fep->ev_err = FEC_ERR_EVENT_MSK;
+
+       return 0;
+}
+
+static int allocate_bd(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       const struct fs_platform_info *fpi = fep->fpi;
+       
+       fep->ring_base = dma_alloc_coherent(fep->dev,
+                                           (fpi->tx_ring + fpi->rx_ring) *
+                                           sizeof(cbd_t), &fep->ring_mem_addr,
+                                           GFP_KERNEL);
+       if (fep->ring_base == NULL)
+               return -ENOMEM;
+
+       return 0;
+}
+
+static void free_bd(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       const struct fs_platform_info *fpi = fep->fpi;
+
+       if(fep->ring_base)
+               dma_free_coherent(fep->dev, (fpi->tx_ring + fpi->rx_ring)
+                                       * sizeof(cbd_t),
+                                       fep->ring_base,
+                                       fep->ring_mem_addr);
+}
+
+static void cleanup_data(struct net_device *dev)
+{
+       /* nothing */
+}
+
+static void set_promiscuous_mode(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fec_t *fecp = fep->fec.fecp;
+
+       FS(fecp, r_cntrl, FEC_RCNTRL_PROM);
+}
+
+static void set_multicast_start(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+
+       fep->fec.hthi = 0;
+       fep->fec.htlo = 0;
+}
+
+static void set_multicast_one(struct net_device *dev, const u8 *mac)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       int temp, hash_index, i, j;
+       u32 crc, csrVal;
+       u8 byte, msb;
+
+       crc = 0xffffffff;
+       for (i = 0; i < 6; i++) {
+               byte = mac[i];
+               for (j = 0; j < 8; j++) {
+                       msb = crc >> 31;
+                       crc <<= 1;
+                       if (msb ^ (byte & 0x1))
+                               crc ^= FEC_CRC_POLY;
+                       byte >>= 1;
+               }
+       }
+
+       temp = (crc & 0x3f) >> 1;
+       hash_index = ((temp & 0x01) << 4) |
+                    ((temp & 0x02) << 2) |
+                    ((temp & 0x04)) |
+                    ((temp & 0x08) >> 2) |
+                    ((temp & 0x10) >> 4);
+       csrVal = 1 << hash_index;
+       if (crc & 1)
+               fep->fec.hthi |= csrVal;
+       else
+               fep->fec.htlo |= csrVal;
+}
+
+static void set_multicast_finish(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fec_t *fecp = fep->fec.fecp;
+
+       /* if all multi or too many multicasts; just enable all */
+       if ((dev->flags & IFF_ALLMULTI) != 0 ||
+           dev->mc_count > FEC_MAX_MULTICAST_ADDRS) {
+               fep->fec.hthi = 0xffffffffU;
+               fep->fec.htlo = 0xffffffffU;
+       }
+
+       FC(fecp, r_cntrl, FEC_RCNTRL_PROM);
+       FW(fecp, hash_table_high, fep->fec.hthi);
+       FW(fecp, hash_table_low, fep->fec.htlo);
+}
+
+static void set_multicast_list(struct net_device *dev)
+{
+       struct dev_mc_list *pmc;
+
+       if ((dev->flags & IFF_PROMISC) == 0) {
+               set_multicast_start(dev);
+               for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
+                       set_multicast_one(dev, pmc->dmi_addr);
+               set_multicast_finish(dev);
+       } else
+               set_promiscuous_mode(dev);
+}
+
+static void restart(struct net_device *dev)
+{
+#ifdef CONFIG_DUET
+       immap_t *immap = fs_enet_immap;
+       u32 cptr;
+#endif
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fec_t *fecp = fep->fec.fecp;
+       const struct fs_platform_info *fpi = fep->fpi;
+       dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
+       int r;
+       u32 addrhi, addrlo;
+
+       r = whack_reset(fep->fec.fecp);
+       if (r != 0)
+               printk(KERN_ERR DRV_MODULE_NAME
+                               ": %s FEC Reset FAILED!\n", dev->name);
+
+       /*
+        * Set station address. 
+        */
+       addrhi = ((u32) dev->dev_addr[0] << 24) |
+                ((u32) dev->dev_addr[1] << 16) |
+                ((u32) dev->dev_addr[2] <<  8) |
+                 (u32) dev->dev_addr[3];
+       addrlo = ((u32) dev->dev_addr[4] << 24) |
+                ((u32) dev->dev_addr[5] << 16);
+       FW(fecp, addr_low, addrhi);
+       FW(fecp, addr_high, addrlo);
+
+       /*
+        * Reset all multicast. 
+        */
+       FW(fecp, hash_table_high, fep->fec.hthi);
+       FW(fecp, hash_table_low, fep->fec.htlo);
+
+       /*
+        * Set maximum receive buffer size. 
+        */
+       FW(fecp, r_buff_size, PKT_MAXBLR_SIZE);
+       FW(fecp, r_hash, PKT_MAXBUF_SIZE);
+
+       /* get physical address */
+       rx_bd_base_phys = fep->ring_mem_addr;
+       tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
+
+       /*
+        * Set receive and transmit descriptor base. 
+        */
+       FW(fecp, r_des_start, rx_bd_base_phys);
+       FW(fecp, x_des_start, tx_bd_base_phys);
+
+       fs_init_bds(dev);
+
+       /*
+        * Enable big endian and don't care about SDMA FC. 
+        */
+       FW(fecp, fun_code, 0x78000000);
+
+       /*
+        * Set MII speed. 
+        */
+       FW(fecp, mii_speed, fep->mii_bus->fec.mii_speed);
+
+       /*
+        * Clear any outstanding interrupt. 
+        */
+       FW(fecp, ievent, 0xffc0);
+       FW(fecp, ivec, (fep->interrupt / 2) << 29);
+       
+
+       /*
+        * adjust to speed (only for DUET & RMII) 
+        */
+#ifdef CONFIG_DUET
+       if (fpi->use_rmii) {
+               cptr = in_be32(&immap->im_cpm.cp_cptr);
+               switch (fs_get_fec_index(fpi->fs_no)) {
+               case 0:
+                       cptr |= 0x100;
+                       if (fep->speed == 10)
+                               cptr |= 0x0000010;
+                       else if (fep->speed == 100)
+                               cptr &= ~0x0000010;
+                       break;
+               case 1:
+                       cptr |= 0x80;
+                       if (fep->speed == 10)
+                               cptr |= 0x0000008;
+                       else if (fep->speed == 100)
+                               cptr &= ~0x0000008;
+                       break;
+               default:
+                       BUG();  /* should never happen */
+                       break;
+               }
+               out_be32(&immap->im_cpm.cp_cptr, cptr);
+       }
+#endif
+
+       FW(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
+       /*
+        * adjust to duplex mode 
+        */
+       if (fep->duplex) {
+               FC(fecp, r_cntrl, FEC_RCNTRL_DRT);
+               FS(fecp, x_cntrl, FEC_TCNTRL_FDEN);     /* FD enable */
+       } else {
+               FS(fecp, r_cntrl, FEC_RCNTRL_DRT);
+               FC(fecp, x_cntrl, FEC_TCNTRL_FDEN);     /* FD disable */
+       }
+
+       /*
+        * Enable interrupts we wish to service. 
+        */
+       FW(fecp, imask, FEC_ENET_TXF | FEC_ENET_TXB |
+          FEC_ENET_RXF | FEC_ENET_RXB);
+
+       /*
+        * And last, enable the transmit and receive processing. 
+        */
+       FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
+       FW(fecp, r_des_active, 0x01000000);
+}
+
+static void stop(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fec_t *fecp = fep->fec.fecp;
+       struct fs_enet_mii_bus *bus = fep->mii_bus;
+       const struct fs_mii_bus_info *bi = bus->bus_info;
+       int i;
+
+       if ((FR(fecp, ecntrl) & FEC_ECNTRL_ETHER_EN) == 0)
+               return;         /* already down */
+
+       FW(fecp, x_cntrl, 0x01);        /* Graceful transmit stop */
+       for (i = 0; ((FR(fecp, ievent) & 0x10000000) == 0) &&
+            i < FEC_RESET_DELAY; i++)
+               udelay(1);
+
+       if (i == FEC_RESET_DELAY)
+               printk(KERN_WARNING DRV_MODULE_NAME
+                      ": %s FEC timeout on graceful transmit stop\n",
+                      dev->name);
+       /*
+        * Disable FEC. Let only MII interrupts. 
+        */
+       FW(fecp, imask, 0);
+       FC(fecp, ecntrl, FEC_ECNTRL_ETHER_EN);
+
+       fs_cleanup_bds(dev);
+
+       /* shut down FEC1? that's where the mii bus is */
+       if (fep->fec.idx == 0 && bus->refs > 1 && bi->method == fsmii_fec) {
+               FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
+               FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
+               FW(fecp, ievent, FEC_ENET_MII);
+               FW(fecp, mii_speed, bus->fec.mii_speed);
+       }
+}
+
+static void pre_request_irq(struct net_device *dev, int irq)
+{
+       immap_t *immap = fs_enet_immap;
+       u32 siel;
+
+       /* SIU interrupt */
+       if (irq >= SIU_IRQ0 && irq < SIU_LEVEL7) {
+
+               siel = in_be32(&immap->im_siu_conf.sc_siel);
+               if ((irq & 1) == 0)
+                       siel |= (0x80000000 >> irq);
+               else
+                       siel &= ~(0x80000000 >> (irq & ~1));
+               out_be32(&immap->im_siu_conf.sc_siel, siel);
+       }
+}
+
+static void post_free_irq(struct net_device *dev, int irq)
+{
+       /* nothing */
+}
+
+static void napi_clear_rx_event(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fec_t *fecp = fep->fec.fecp;
+
+       FW(fecp, ievent, FEC_NAPI_RX_EVENT_MSK);
+}
+
+static void napi_enable_rx(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fec_t *fecp = fep->fec.fecp;
+
+       FS(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
+}
+
+static void napi_disable_rx(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fec_t *fecp = fep->fec.fecp;
+
+       FC(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
+}
+
+static void rx_bd_done(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fec_t *fecp = fep->fec.fecp;
+
+       FW(fecp, r_des_active, 0x01000000);
+}
+
+static void tx_kickstart(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fec_t *fecp = fep->fec.fecp;
+
+       FW(fecp, x_des_active, 0x01000000);
+}
+
+static u32 get_int_events(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fec_t *fecp = fep->fec.fecp;
+
+       return FR(fecp, ievent) & FR(fecp, imask);
+}
+
+static void clear_int_events(struct net_device *dev, u32 int_events)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       fec_t *fecp = fep->fec.fecp;
+
+       FW(fecp, ievent, int_events);
+}
+
+static void ev_error(struct net_device *dev, u32 int_events)
+{
+       printk(KERN_WARNING DRV_MODULE_NAME
+              ": %s FEC ERROR(s) 0x%x\n", dev->name, int_events);
+}
+
+int get_regs(struct net_device *dev, void *p, int *sizep)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+
+       if (*sizep < sizeof(fec_t))
+               return -EINVAL;
+
+       memcpy_fromio(p, fep->fec.fecp, sizeof(fec_t));
+
+       return 0;
+}
+
+int get_regs_len(struct net_device *dev)
+{
+       return sizeof(fec_t);
+}
+
+void tx_restart(struct net_device *dev)
+{
+       /* nothing */
+}
+
+/*************************************************************************/
+
+const struct fs_ops fs_fec_ops = {
+       .setup_data             = setup_data,
+       .cleanup_data           = cleanup_data,
+       .set_multicast_list     = set_multicast_list,
+       .restart                = restart,
+       .stop                   = stop,
+       .pre_request_irq        = pre_request_irq,
+       .post_free_irq          = post_free_irq,
+       .napi_clear_rx_event    = napi_clear_rx_event,
+       .napi_enable_rx         = napi_enable_rx,
+       .napi_disable_rx        = napi_disable_rx,
+       .rx_bd_done             = rx_bd_done,
+       .tx_kickstart           = tx_kickstart,
+       .get_int_events         = get_int_events,
+       .clear_int_events       = clear_int_events,
+       .ev_error               = ev_error,
+       .get_regs               = get_regs,
+       .get_regs_len           = get_regs_len,
+       .tx_restart             = tx_restart,
+       .allocate_bd            = allocate_bd,
+       .free_bd                = free_bd,
+};
+
+/***********************************************************************/
+
+static int mii_read(struct fs_enet_mii_bus *bus, int phy_id, int location)
+{
+       fec_t *fecp = bus->fec.fecp;
+       int i, ret = -1;
+
+       if ((FR(fecp, r_cntrl) & FEC_RCNTRL_MII_MODE) == 0)
+               BUG();
+
+       /* Add PHY address to register command.  */
+       FW(fecp, mii_data, (phy_id << 23) | mk_mii_read(location));
+
+       for (i = 0; i < FEC_MII_LOOPS; i++)
+               if ((FR(fecp, ievent) & FEC_ENET_MII) != 0)
+                       break;
+
+       if (i < FEC_MII_LOOPS) {
+               FW(fecp, ievent, FEC_ENET_MII);
+               ret = FR(fecp, mii_data) & 0xffff;
+       }
+
+       return ret;
+}
+
+static void mii_write(struct fs_enet_mii_bus *bus, int phy_id, int location, int value)
+{
+       fec_t *fecp = bus->fec.fecp;
+       int i;
+
+       /* this must never happen */
+       if ((FR(fecp, r_cntrl) & FEC_RCNTRL_MII_MODE) == 0)
+               BUG();
+
+       /* Add PHY address to register command.  */
+       FW(fecp, mii_data, (phy_id << 23) | mk_mii_write(location, value));
+
+       for (i = 0; i < FEC_MII_LOOPS; i++)
+               if ((FR(fecp, ievent) & FEC_ENET_MII) != 0)
+                       break;
+
+       if (i < FEC_MII_LOOPS)
+               FW(fecp, ievent, FEC_ENET_MII);
+}
+
+int fs_mii_fec_init(struct fs_enet_mii_bus *bus)
+{
+       bd_t *bd = (bd_t *)__res;
+       const struct fs_mii_bus_info *bi = bus->bus_info;
+       fec_t *fecp;
+
+       if (bi->id != 0)
+               return -1;
+
+       bus->fec.fecp = &((immap_t *)fs_enet_immap)->im_cpm.cp_fec;
+       bus->fec.mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2)
+                               & 0x3F) << 1;
+
+       fecp = bus->fec.fecp;
+
+       FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
+       FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
+       FW(fecp, ievent, FEC_ENET_MII);
+       FW(fecp, mii_speed, bus->fec.mii_speed);
+
+       bus->mii_read = mii_read;
+       bus->mii_write = mii_write;
+
+       return 0;
+}
diff --git a/drivers/net/fs_enet/mac-scc.c b/drivers/net/fs_enet/mac-scc.c
new file mode 100644 (file)
index 0000000..d8c6e9c
--- /dev/null
@@ -0,0 +1,524 @@
+/*
+ * Ethernet on Serial Communications Controller (SCC) driver for Motorola MPC8xx and MPC82xx.
+ *
+ * Copyright (c) 2003 Intracom S.A. 
+ *  by Pantelis Antoniou <panto@intracom.gr>
+ * 
+ * 2005 (c) MontaVista Software, Inc. 
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License 
+ * version 2. This program is licensed "as is" without any warranty of any 
+ * kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <linux/ptrace.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/spinlock.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/bitops.h>
+#include <linux/fs.h>
+
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+
+#ifdef CONFIG_8xx
+#include <asm/8xx_immap.h>
+#include <asm/pgtable.h>
+#include <asm/mpc8xx.h>
+#include <asm/commproc.h>
+#endif
+
+#include "fs_enet.h"
+
+/*************************************************/
+
+#if defined(CONFIG_CPM1)
+/* for a 8xx __raw_xxx's are sufficient */
+#define __fs_out32(addr, x)    __raw_writel(x, addr)
+#define __fs_out16(addr, x)    __raw_writew(x, addr)
+#define __fs_out8(addr, x)     __raw_writeb(x, addr)
+#define __fs_in32(addr)        __raw_readl(addr)
+#define __fs_in16(addr)        __raw_readw(addr)
+#define __fs_in8(addr) __raw_readb(addr)
+#else
+/* for others play it safe */
+#define __fs_out32(addr, x)    out_be32(addr, x)
+#define __fs_out16(addr, x)    out_be16(addr, x)
+#define __fs_in32(addr)        in_be32(addr)
+#define __fs_in16(addr)        in_be16(addr)
+#endif
+
+/* write, read, set bits, clear bits */
+#define W32(_p, _m, _v) __fs_out32(&(_p)->_m, (_v))
+#define R32(_p, _m)     __fs_in32(&(_p)->_m)
+#define S32(_p, _m, _v) W32(_p, _m, R32(_p, _m) | (_v))
+#define C32(_p, _m, _v) W32(_p, _m, R32(_p, _m) & ~(_v))
+
+#define W16(_p, _m, _v) __fs_out16(&(_p)->_m, (_v))
+#define R16(_p, _m)     __fs_in16(&(_p)->_m)
+#define S16(_p, _m, _v) W16(_p, _m, R16(_p, _m) | (_v))
+#define C16(_p, _m, _v) W16(_p, _m, R16(_p, _m) & ~(_v))
+
+#define W8(_p, _m, _v)  __fs_out8(&(_p)->_m, (_v))
+#define R8(_p, _m)      __fs_in8(&(_p)->_m)
+#define S8(_p, _m, _v)  W8(_p, _m, R8(_p, _m) | (_v))
+#define C8(_p, _m, _v)  W8(_p, _m, R8(_p, _m) & ~(_v))
+
+#define SCC_MAX_MULTICAST_ADDRS        64
+
+/*
+ * Delay to wait for SCC reset command to complete (in us) 
+ */
+#define SCC_RESET_DELAY                50
+#define MAX_CR_CMD_LOOPS       10000
+
+static inline int scc_cr_cmd(struct fs_enet_private *fep, u32 op)
+{
+       cpm8xx_t *cpmp = &((immap_t *)fs_enet_immap)->im_cpm;
+       u32 v, ch;
+       int i = 0;
+
+       ch = fep->scc.idx << 2;
+       v = mk_cr_cmd(ch, op);
+       W16(cpmp, cp_cpcr, v | CPM_CR_FLG);
+       for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
+               if ((R16(cpmp, cp_cpcr) & CPM_CR_FLG) == 0)
+                       break;
+
+       if (i >= MAX_CR_CMD_LOOPS) {
+               printk(KERN_ERR "%s(): Not able to issue CPM command\n",
+                       __FUNCTION__);
+               return 1;
+       }
+       return 0;
+}
+
+static int do_pd_setup(struct fs_enet_private *fep)
+{
+       struct platform_device *pdev = to_platform_device(fep->dev);
+       struct resource *r;
+
+       /* Fill out IRQ field */
+       fep->interrupt = platform_get_irq_byname(pdev, "interrupt");
+
+       r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
+       fep->scc.sccp = (void *)r->start;
+
+       if (fep->scc.sccp == NULL)
+               return -EINVAL;
+
+       r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pram");
+       fep->scc.ep = (void *)r->start;
+
+       if (fep->scc.ep == NULL)
+               return -EINVAL;
+
+       return 0;
+}
+
+#define SCC_NAPI_RX_EVENT_MSK  (SCCE_ENET_RXF | SCCE_ENET_RXB)
+#define SCC_RX_EVENT           (SCCE_ENET_RXF)
+#define SCC_TX_EVENT           (SCCE_ENET_TXB)
+#define SCC_ERR_EVENT_MSK      (SCCE_ENET_TXE | SCCE_ENET_BSY)
+
+static int setup_data(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       const struct fs_platform_info *fpi = fep->fpi;
+
+       fep->scc.idx = fs_get_scc_index(fpi->fs_no);
+       if ((unsigned int)fep->fcc.idx > 4)     /* max 4 SCCs */
+               return -EINVAL;
+
+       do_pd_setup(fep);
+
+       fep->scc.hthi = 0;
+       fep->scc.htlo = 0;
+
+       fep->ev_napi_rx = SCC_NAPI_RX_EVENT_MSK;
+       fep->ev_rx = SCC_RX_EVENT;
+       fep->ev_tx = SCC_TX_EVENT;
+       fep->ev_err = SCC_ERR_EVENT_MSK;
+
+       return 0;
+}
+
+static int allocate_bd(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       const struct fs_platform_info *fpi = fep->fpi;
+
+       fep->ring_mem_addr = cpm_dpalloc((fpi->tx_ring + fpi->rx_ring) *
+                                        sizeof(cbd_t), 8);
+       if (IS_DPERR(fep->ring_mem_addr))
+               return -ENOMEM;
+
+       fep->ring_base = cpm_dpram_addr(fep->ring_mem_addr);
+
+       return 0;
+}
+
+static void free_bd(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+
+       if (fep->ring_base)
+               cpm_dpfree(fep->ring_mem_addr);
+}
+
+static void cleanup_data(struct net_device *dev)
+{
+       /* nothing */
+}
+
+static void set_promiscuous_mode(struct net_device *dev)
+{                              
+       struct fs_enet_private *fep = netdev_priv(dev);
+       scc_t *sccp = fep->scc.sccp;
+
+       S16(sccp, scc_psmr, SCC_PSMR_PRO);
+}
+
+static void set_multicast_start(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       scc_enet_t *ep = fep->scc.ep;
+
+       W16(ep, sen_gaddr1, 0);
+       W16(ep, sen_gaddr2, 0);
+       W16(ep, sen_gaddr3, 0);
+       W16(ep, sen_gaddr4, 0);
+}
+
+static void set_multicast_one(struct net_device *dev, const u8 * mac)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       scc_enet_t *ep = fep->scc.ep;
+       u16 taddrh, taddrm, taddrl;
+
+       taddrh = ((u16) mac[5] << 8) | mac[4];
+       taddrm = ((u16) mac[3] << 8) | mac[2];
+       taddrl = ((u16) mac[1] << 8) | mac[0];
+
+       W16(ep, sen_taddrh, taddrh);
+       W16(ep, sen_taddrm, taddrm);
+       W16(ep, sen_taddrl, taddrl);
+       scc_cr_cmd(fep, CPM_CR_SET_GADDR);
+}
+
+static void set_multicast_finish(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       scc_t *sccp = fep->scc.sccp;
+       scc_enet_t *ep = fep->scc.ep;
+
+       /* clear promiscuous always */
+       C16(sccp, scc_psmr, SCC_PSMR_PRO);
+
+       /* if all multi or too many multicasts; just enable all */
+       if ((dev->flags & IFF_ALLMULTI) != 0 ||
+           dev->mc_count > SCC_MAX_MULTICAST_ADDRS) {
+
+               W16(ep, sen_gaddr1, 0xffff);
+               W16(ep, sen_gaddr2, 0xffff);
+               W16(ep, sen_gaddr3, 0xffff);
+               W16(ep, sen_gaddr4, 0xffff);
+       }
+}
+
+static void set_multicast_list(struct net_device *dev)
+{
+       struct dev_mc_list *pmc;
+
+       if ((dev->flags & IFF_PROMISC) == 0) {
+               set_multicast_start(dev);
+               for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
+                       set_multicast_one(dev, pmc->dmi_addr);
+               set_multicast_finish(dev);
+       } else
+               set_promiscuous_mode(dev);
+}
+
+/*
+ * This function is called to start or restart the FEC during a link
+ * change.  This only happens when switching between half and full
+ * duplex.
+ */
+static void restart(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       scc_t *sccp = fep->scc.sccp;
+       scc_enet_t *ep = fep->scc.ep;
+       const struct fs_platform_info *fpi = fep->fpi;
+       u16 paddrh, paddrm, paddrl;
+       const unsigned char *mac;
+       int i;
+
+       C32(sccp, scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+
+       /* clear everything (slow & steady does it) */
+       for (i = 0; i < sizeof(*ep); i++)
+               __fs_out8((char *)ep + i, 0);
+
+       /* point to bds */
+       W16(ep, sen_genscc.scc_rbase, fep->ring_mem_addr);
+       W16(ep, sen_genscc.scc_tbase,
+           fep->ring_mem_addr + sizeof(cbd_t) * fpi->rx_ring);
+
+       /* Initialize function code registers for big-endian.
+        */
+       W8(ep, sen_genscc.scc_rfcr, SCC_EB);
+       W8(ep, sen_genscc.scc_tfcr, SCC_EB);
+
+       /* Set maximum bytes per receive buffer.
+        * This appears to be an Ethernet frame size, not the buffer
+        * fragment size.  It must be a multiple of four.
+        */
+       W16(ep, sen_genscc.scc_mrblr, 0x5f0);
+
+       /* Set CRC preset and mask.
+        */
+       W32(ep, sen_cpres, 0xffffffff);
+       W32(ep, sen_cmask, 0xdebb20e3);
+
+       W32(ep, sen_crcec, 0);  /* CRC Error counter */
+       W32(ep, sen_alec, 0);   /* alignment error counter */
+       W32(ep, sen_disfc, 0);  /* discard frame counter */
+
+       W16(ep, sen_pads, 0x8888);      /* Tx short frame pad character */
+       W16(ep, sen_retlim, 15);        /* Retry limit threshold */
+
+       W16(ep, sen_maxflr, 0x5ee);     /* maximum frame length register */
+
+       W16(ep, sen_minflr, PKT_MINBUF_SIZE);   /* minimum frame length register */
+
+       W16(ep, sen_maxd1, 0x000005f0); /* maximum DMA1 length */
+       W16(ep, sen_maxd2, 0x000005f0); /* maximum DMA2 length */
+
+       /* Clear hash tables.
+        */
+       W16(ep, sen_gaddr1, 0);
+       W16(ep, sen_gaddr2, 0);
+       W16(ep, sen_gaddr3, 0);
+       W16(ep, sen_gaddr4, 0);
+       W16(ep, sen_iaddr1, 0);
+       W16(ep, sen_iaddr2, 0);
+       W16(ep, sen_iaddr3, 0);
+       W16(ep, sen_iaddr4, 0);
+
+       /* set address 
+        */
+       mac = dev->dev_addr;
+       paddrh = ((u16) mac[5] << 8) | mac[4];
+       paddrm = ((u16) mac[3] << 8) | mac[2];
+       paddrl = ((u16) mac[1] << 8) | mac[0];
+
+       W16(ep, sen_paddrh, paddrh);
+       W16(ep, sen_paddrm, paddrm);
+       W16(ep, sen_paddrl, paddrl);
+
+       W16(ep, sen_pper, 0);
+       W16(ep, sen_taddrl, 0);
+       W16(ep, sen_taddrm, 0);
+       W16(ep, sen_taddrh, 0);
+
+       fs_init_bds(dev);
+
+       scc_cr_cmd(fep, CPM_CR_INIT_TRX);
+
+       W16(sccp, scc_scce, 0xffff);
+
+       /* Enable interrupts we wish to service. 
+        */
+       W16(sccp, scc_sccm, SCCE_ENET_TXE | SCCE_ENET_RXF | SCCE_ENET_TXB);
+
+       /* Set GSMR_H to enable all normal operating modes.
+        * Set GSMR_L to enable Ethernet to MC68160.
+        */
+       W32(sccp, scc_gsmrh, 0);
+       W32(sccp, scc_gsmrl,
+           SCC_GSMRL_TCI | SCC_GSMRL_TPL_48 | SCC_GSMRL_TPP_10 |
+           SCC_GSMRL_MODE_ENET);
+
+       /* Set sync/delimiters.
+        */
+       W16(sccp, scc_dsr, 0xd555);
+
+       /* Set processing mode.  Use Ethernet CRC, catch broadcast, and
+        * start frame search 22 bit times after RENA.
+        */
+       W16(sccp, scc_psmr, SCC_PSMR_ENCRC | SCC_PSMR_NIB22);
+
+       /* Set full duplex mode if needed */
+       if (fep->duplex)
+               S16(sccp, scc_psmr, SCC_PSMR_LPB | SCC_PSMR_FDE);
+
+       S32(sccp, scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+}
+
+static void stop(struct net_device *dev)       
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       scc_t *sccp = fep->scc.sccp;
+       int i;
+
+       for (i = 0; (R16(sccp, scc_sccm) == 0) && i < SCC_RESET_DELAY; i++)
+               udelay(1);
+
+       if (i == SCC_RESET_DELAY)
+               printk(KERN_WARNING DRV_MODULE_NAME
+                      ": %s SCC timeout on graceful transmit stop\n",
+                      dev->name);
+
+       W16(sccp, scc_sccm, 0);
+       C32(sccp, scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+
+       fs_cleanup_bds(dev);
+}
+
+static void pre_request_irq(struct net_device *dev, int irq)
+{
+       immap_t *immap = fs_enet_immap;
+       u32 siel;
+
+       /* SIU interrupt */
+       if (irq >= SIU_IRQ0 && irq < SIU_LEVEL7) {
+
+               siel = in_be32(&immap->im_siu_conf.sc_siel);
+               if ((irq & 1) == 0)
+                       siel |= (0x80000000 >> irq);
+               else
+                       siel &= ~(0x80000000 >> (irq & ~1));
+               out_be32(&immap->im_siu_conf.sc_siel, siel);
+       }
+}
+
+static void post_free_irq(struct net_device *dev, int irq)
+{
+       /* nothing */
+}
+
+static void napi_clear_rx_event(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       scc_t *sccp = fep->scc.sccp;
+
+       W16(sccp, scc_scce, SCC_NAPI_RX_EVENT_MSK);
+}
+
+static void napi_enable_rx(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       scc_t *sccp = fep->scc.sccp;
+
+       S16(sccp, scc_sccm, SCC_NAPI_RX_EVENT_MSK);
+}
+
+static void napi_disable_rx(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       scc_t *sccp = fep->scc.sccp;
+
+       C16(sccp, scc_sccm, SCC_NAPI_RX_EVENT_MSK);
+}
+
+static void rx_bd_done(struct net_device *dev)
+{
+       /* nothing */
+}
+
+static void tx_kickstart(struct net_device *dev)
+{
+       /* nothing */
+}
+
+static u32 get_int_events(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       scc_t *sccp = fep->scc.sccp;
+
+       return (u32) R16(sccp, scc_scce);
+}
+
+static void clear_int_events(struct net_device *dev, u32 int_events)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+       scc_t *sccp = fep->scc.sccp;
+
+       W16(sccp, scc_scce, int_events & 0xffff);
+}
+
+static void ev_error(struct net_device *dev, u32 int_events)
+{
+       printk(KERN_WARNING DRV_MODULE_NAME
+              ": %s SCC ERROR(s) 0x%x\n", dev->name, int_events);
+}
+
+static int get_regs(struct net_device *dev, void *p, int *sizep)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+
+       if (*sizep < sizeof(scc_t) + sizeof(scc_enet_t))
+               return -EINVAL;
+
+       memcpy_fromio(p, fep->scc.sccp, sizeof(scc_t));
+       p = (char *)p + sizeof(scc_t);
+
+       memcpy_fromio(p, fep->scc.ep, sizeof(scc_enet_t));
+
+       return 0;
+}
+
+static int get_regs_len(struct net_device *dev)
+{
+       return sizeof(scc_t) + sizeof(scc_enet_t);
+}
+
+static void tx_restart(struct net_device *dev)
+{
+       struct fs_enet_private *fep = netdev_priv(dev);
+
+       scc_cr_cmd(fep, CPM_CR_RESTART_TX);
+}
+
+/*************************************************************************/
+
+const struct fs_ops fs_scc_ops = {
+       .setup_data             = setup_data,
+       .cleanup_data           = cleanup_data,
+       .set_multicast_list     = set_multicast_list,
+       .restart                = restart,
+       .stop                   = stop,
+       .pre_request_irq        = pre_request_irq,
+       .post_free_irq          = post_free_irq,
+       .napi_clear_rx_event    = napi_clear_rx_event,
+       .napi_enable_rx         = napi_enable_rx,
+       .napi_disable_rx        = napi_disable_rx,
+       .rx_bd_done             = rx_bd_done,
+       .tx_kickstart           = tx_kickstart,
+       .get_int_events         = get_int_events,
+       .clear_int_events       = clear_int_events,
+       .ev_error               = ev_error,
+       .get_regs               = get_regs,
+       .get_regs_len           = get_regs_len,
+       .tx_restart             = tx_restart,
+       .allocate_bd            = allocate_bd,
+       .free_bd                = free_bd,
+};
diff --git a/drivers/net/fs_enet/mii-bitbang.c b/drivers/net/fs_enet/mii-bitbang.c
new file mode 100644 (file)
index 0000000..24a5e2e
--- /dev/null
@@ -0,0 +1,405 @@
+/*
+ * Combined Ethernet driver for Motorola MPC8xx and MPC82xx.
+ *
+ * Copyright (c) 2003 Intracom S.A. 
+ *  by Pantelis Antoniou <panto@intracom.gr>
+ * 
+ * 2005 (c) MontaVista Software, Inc. 
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License 
+ * version 2. This program is licensed "as is" without any warranty of any 
+ * kind, whether express or implied.
+ */
+
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <linux/ptrace.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/spinlock.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/bitops.h>
+
+#include <asm/pgtable.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+
+#include "fs_enet.h"
+
+#ifdef CONFIG_8xx
+static int bitbang_prep_bit(u8 **dirp, u8 **datp, u8 *mskp, int port, int bit)
+{
+       immap_t *im = (immap_t *)fs_enet_immap;
+       void *dir, *dat, *ppar;
+       int adv;
+       u8 msk;
+
+       switch (port) {
+               case fsiop_porta:
+                       dir = &im->im_ioport.iop_padir;
+                       dat = &im->im_ioport.iop_padat;
+                       ppar = &im->im_ioport.iop_papar;
+                       break;
+
+               case fsiop_portb:
+                       dir = &im->im_cpm.cp_pbdir;
+                       dat = &im->im_cpm.cp_pbdat;
+                       ppar = &im->im_cpm.cp_pbpar;
+                       break;
+
+               case fsiop_portc:
+                       dir = &im->im_ioport.iop_pcdir;
+                       dat = &im->im_ioport.iop_pcdat;
+                       ppar = &im->im_ioport.iop_pcpar;
+                       break;
+
+               case fsiop_portd:
+                       dir = &im->im_ioport.iop_pddir;
+                       dat = &im->im_ioport.iop_pddat;
+                       ppar = &im->im_ioport.iop_pdpar;
+                       break;
+
+               case fsiop_porte:
+                       dir = &im->im_cpm.cp_pedir;
+                       dat = &im->im_cpm.cp_pedat;
+                       ppar = &im->im_cpm.cp_pepar;
+                       break;
+
+               default:
+                       printk(KERN_ERR DRV_MODULE_NAME
+                              "Illegal port value %d!\n", port);
+                       return -EINVAL;
+       }
+
+       adv = bit >> 3;
+       dir = (char *)dir + adv;
+       dat = (char *)dat + adv;
+       ppar = (char *)ppar + adv;
+
+       msk = 1 << (7 - (bit & 7));
+       if ((in_8(ppar) & msk) != 0) {
+               printk(KERN_ERR DRV_MODULE_NAME
+                      "pin %d on port %d is not general purpose!\n", bit, port);
+               return -EINVAL;
+       }
+
+       *dirp = dir;
+       *datp = dat;
+       *mskp = msk;
+
+       return 0;
+}
+#endif
+
+#ifdef CONFIG_8260
+static int bitbang_prep_bit(u8 **dirp, u8 **datp, u8 *mskp, int port, int bit)
+{
+       iop_cpm2_t *io = &((cpm2_map_t *)fs_enet_immap)->im_ioport;
+       void *dir, *dat, *ppar;
+       int adv;
+       u8 msk;
+
+       switch (port) {
+               case fsiop_porta:
+                       dir = &io->iop_pdira;
+                       dat = &io->iop_pdata;
+                       ppar = &io->iop_ppara;
+                       break;
+
+               case fsiop_portb:
+                       dir = &io->iop_pdirb;
+                       dat = &io->iop_pdatb;
+                       ppar = &io->iop_pparb;
+                       break;
+
+               case fsiop_portc:
+                       dir = &io->iop_pdirc;
+                       dat = &io->iop_pdatc;
+                       ppar = &io->iop_pparc;
+                       break;
+
+               case fsiop_portd:
+                       dir = &io->iop_pdird;
+                       dat = &io->iop_pdatd;
+                       ppar = &io->iop_ppard;
+                       break;
+
+               default:
+                       printk(KERN_ERR DRV_MODULE_NAME
+                              "Illegal port value %d!\n", port);
+                       return -EINVAL;
+       }
+
+       adv = bit >> 3;
+       dir = (char *)dir + adv;
+       dat = (char *)dat + adv;
+       ppar = (char *)ppar + adv;
+
+       msk = 1 << (7 - (bit & 7));
+       if ((in_8(ppar) & msk) != 0) {
+               printk(KERN_ERR DRV_MODULE_NAME
+                      "pin %d on port %d is not general purpose!\n", bit, port);
+               return -EINVAL;
+       }
+
+       *dirp = dir;
+       *datp = dat;
+       *mskp = msk;
+
+       return 0;
+}
+#endif
+
+static inline void bb_set(u8 *p, u8 m)
+{
+       out_8(p, in_8(p) | m);
+}
+
+static inline void bb_clr(u8 *p, u8 m)
+{
+       out_8(p, in_8(p) & ~m);
+}
+
+static inline int bb_read(u8 *p, u8 m)
+{
+       return (in_8(p) & m) != 0;
+}
+
+static inline void mdio_active(struct fs_enet_mii_bus *bus)
+{
+       bb_set(bus->bitbang.mdio_dir, bus->bitbang.mdio_msk);
+}
+
+static inline void mdio_tristate(struct fs_enet_mii_bus *bus)
+{
+       bb_clr(bus->bitbang.mdio_dir, bus->bitbang.mdio_msk);
+}
+
+static inline int mdio_read(struct fs_enet_mii_bus *bus)
+{
+       return bb_read(bus->bitbang.mdio_dat, bus->bitbang.mdio_msk);
+}
+
+static inline void mdio(struct fs_enet_mii_bus *bus, int what)
+{
+       if (what)
+               bb_set(bus->bitbang.mdio_dat, bus->bitbang.mdio_msk);
+       else
+               bb_clr(bus->bitbang.mdio_dat, bus->bitbang.mdio_msk);
+}
+
+static inline void mdc(struct fs_enet_mii_bus *bus, int what)
+{
+       if (what)
+               bb_set(bus->bitbang.mdc_dat, bus->bitbang.mdc_msk);
+       else
+               bb_clr(bus->bitbang.mdc_dat, bus->bitbang.mdc_msk);
+}
+
+static inline void mii_delay(struct fs_enet_mii_bus *bus)
+{
+       udelay(bus->bus_info->i.bitbang.delay);
+}
+
+/* Utility to send the preamble, address, and register (common to read and write). */
+static void bitbang_pre(struct fs_enet_mii_bus *bus, int read, u8 addr, u8 reg)
+{
+       int j;
+
+       /*
+        * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
+        * The IEEE spec says this is a PHY optional requirement.  The AMD
+        * 79C874 requires one after power up and one after a MII communications
+        * error.  This means that we are doing more preambles than we need,
+        * but it is safer and will be much more robust.
+        */
+
+       mdio_active(bus);
+       mdio(bus, 1);
+       for (j = 0; j < 32; j++) {
+               mdc(bus, 0);
+               mii_delay(bus);
+               mdc(bus, 1);
+               mii_delay(bus);
+       }
+
+       /* send the start bit (01) and the read opcode (10) or write (10) */
+       mdc(bus, 0);
+       mdio(bus, 0);
+       mii_delay(bus);
+       mdc(bus, 1);
+       mii_delay(bus);
+       mdc(bus, 0);
+       mdio(bus, 1);
+       mii_delay(bus);
+       mdc(bus, 1);
+       mii_delay(bus);
+       mdc(bus, 0);
+       mdio(bus, read);
+       mii_delay(bus);
+       mdc(bus, 1);
+       mii_delay(bus);
+       mdc(bus, 0);
+       mdio(bus, !read);
+       mii_delay(bus);
+       mdc(bus, 1);
+       mii_delay(bus);
+
+       /* send the PHY address */
+       for (j = 0; j < 5; j++) {
+               mdc(bus, 0);
+               mdio(bus, (addr & 0x10) != 0);
+               mii_delay(bus);
+               mdc(bus, 1);
+               mii_delay(bus);
+               addr <<= 1;
+       }
+
+       /* send the register address */
+       for (j = 0; j < 5; j++) {
+               mdc(bus, 0);
+               mdio(bus, (reg & 0x10) != 0);
+               mii_delay(bus);
+               mdc(bus, 1);
+               mii_delay(bus);
+               reg <<= 1;
+       }
+}
+
+static int mii_read(struct fs_enet_mii_bus *bus, int phy_id, int location)
+{
+       u16 rdreg;
+       int ret, j;
+       u8 addr = phy_id & 0xff;
+       u8 reg = location & 0xff;
+
+       bitbang_pre(bus, 1, addr, reg);
+
+       /* tri-state our MDIO I/O pin so we can read */
+       mdc(bus, 0);
+       mdio_tristate(bus);
+       mii_delay(bus);
+       mdc(bus, 1);
+       mii_delay(bus);
+
+       /* check the turnaround bit: the PHY should be driving it to zero */
+       if (mdio_read(bus) != 0) {
+               /* PHY didn't drive TA low */
+               for (j = 0; j < 32; j++) {
+                       mdc(bus, 0);
+                       mii_delay(bus);
+                       mdc(bus, 1);
+                       mii_delay(bus);
+               }
+               ret = -1;
+               goto out;
+       }
+
+       mdc(bus, 0);
+       mii_delay(bus);
+
+       /* read 16 bits of register data, MSB first */
+       rdreg = 0;
+       for (j = 0; j < 16; j++) {
+               mdc(bus, 1);
+               mii_delay(bus);
+               rdreg <<= 1;
+               rdreg |= mdio_read(bus);
+               mdc(bus, 0);
+               mii_delay(bus);
+       }
+
+       mdc(bus, 1);
+       mii_delay(bus);
+       mdc(bus, 0);
+       mii_delay(bus);
+       mdc(bus, 1);
+       mii_delay(bus);
+
+       ret = rdreg;
+out:
+       return ret;
+}
+
+static void mii_write(struct fs_enet_mii_bus *bus, int phy_id, int location, int val)
+{
+       int j;
+       u8 addr = phy_id & 0xff;
+       u8 reg = location & 0xff;
+       u16 value = val & 0xffff;
+
+       bitbang_pre(bus, 0, addr, reg);
+
+       /* send the turnaround (10) */
+       mdc(bus, 0);
+       mdio(bus, 1);
+       mii_delay(bus);
+       mdc(bus, 1);
+       mii_delay(bus);
+       mdc(bus, 0);
+       mdio(bus, 0);
+       mii_delay(bus);
+       mdc(bus, 1);
+       mii_delay(bus);
+
+       /* write 16 bits of register data, MSB first */
+       for (j = 0; j < 16; j++) {
+               mdc(bus, 0);
+               mdio(bus, (value & 0x8000) != 0);
+               mii_delay(bus);
+               mdc(bus, 1);
+               mii_delay(bus);
+               value <<= 1;
+       }
+
+       /*
+        * Tri-state the MDIO line.
+        */
+       mdio_tristate(bus);
+       mdc(bus, 0);
+       mii_delay(bus);
+       mdc(bus, 1);
+       mii_delay(bus);
+}
+
+int fs_mii_bitbang_init(struct fs_enet_mii_bus *bus)
+{
+       const struct fs_mii_bus_info *bi = bus->bus_info;
+       int r;
+
+       r = bitbang_prep_bit(&bus->bitbang.mdio_dir,
+                        &bus->bitbang.mdio_dat,
+                        &bus->bitbang.mdio_msk,
+                        bi->i.bitbang.mdio_port,
+                        bi->i.bitbang.mdio_bit);
+       if (r != 0)
+               return r;
+
+       r = bitbang_prep_bit(&bus->bitbang.mdc_dir,
+                        &bus->bitbang.mdc_dat,
+                        &bus->bitbang.mdc_msk,
+                        bi->i.bitbang.mdc_port,
+                        bi->i.bitbang.mdc_bit);
+       if (r != 0)
+               return r;
+
+       bus->mii_read = mii_read;
+       bus->mii_write = mii_write;
+
+       return 0;
+}
diff --git a/drivers/net/fs_enet/mii-fixed.c b/drivers/net/fs_enet/mii-fixed.c
new file mode 100644 (file)
index 0000000..b3e192d
--- /dev/null
@@ -0,0 +1,92 @@
+/*
+ * Combined Ethernet driver for Motorola MPC8xx and MPC82xx.
+ *
+ * Copyright (c) 2003 Intracom S.A. 
+ *  by Pantelis Antoniou <panto@intracom.gr>
+ * 
+ * 2005 (c) MontaVista Software, Inc. 
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License 
+ * version 2. This program is licensed "as is" without any warranty of any 
+ * kind, whether express or implied.
+ */
+
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/string.h>
+#include <linux/ptrace.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/spinlock.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/bitops.h>
+
+#include <asm/pgtable.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+
+#include "fs_enet.h"
+
+static const u16 mii_regs[7] = {
+       0x3100,
+       0x786d,
+       0x0fff,
+       0x0fff,
+       0x01e1,
+       0x45e1,
+       0x0003,
+};
+
+static int mii_read(struct fs_enet_mii_bus *bus, int phy_id, int location)
+{
+       int ret = 0;
+
+       if ((unsigned int)location >= ARRAY_SIZE(mii_regs))
+               return -1;
+
+       if (location != 5)
+               ret = mii_regs[location];
+       else
+               ret = bus->fixed.lpa;
+
+       return ret;
+}
+
+static void mii_write(struct fs_enet_mii_bus *bus, int phy_id, int location, int val)
+{
+       /* do nothing */
+}
+
+int fs_mii_fixed_init(struct fs_enet_mii_bus *bus)
+{
+       const struct fs_mii_bus_info *bi = bus->bus_info;
+
+       bus->fixed.lpa = 0x45e1;        /* default 100Mb, full duplex */
+
+       /* if speed is fixed at 10Mb, remove 100Mb modes */
+       if (bi->i.fixed.speed == 10)
+               bus->fixed.lpa &= ~LPA_100;
+
+       /* if duplex is half, remove full duplex modes */
+       if (bi->i.fixed.duplex == 0)
+               bus->fixed.lpa &= ~LPA_DUPLEX;
+
+       bus->mii_read = mii_read;
+       bus->mii_write = mii_write;
+
+       return 0;
+}
index 85d6dc0..3e9accf 100644 (file)
@@ -390,10 +390,8 @@ static void ax_changedmtu(struct mkiss *ax)
                       "MTU change cancelled.\n",
                       ax->dev->name);
                dev->mtu = ax->mtu;
-               if (xbuff != NULL)
-                       kfree(xbuff);
-               if (rbuff != NULL)
-                       kfree(rbuff);
+               kfree(xbuff);
+               kfree(rbuff);
                return;
        }
 
index 7f583a3..f98ddf0 100644 (file)
@@ -1,12 +1,11 @@
 #
-# Makefile for the IBM PPC4xx EMAC controllers
+# Makefile for the PowerPC 4xx on-chip ethernet driver
 #
 
 obj-$(CONFIG_IBM_EMAC) += ibm_emac.o
 
-ibm_emac-objs := ibm_emac_mal.o ibm_emac_core.o ibm_emac_phy.o
-
-# Only need this if you want to see additional debug messages
-ifeq ($(CONFIG_IBM_EMAC_ERRMSG), y)
-ibm_emac-objs += ibm_emac_debug.o
-endif
+ibm_emac-objs := ibm_emac_mal.o ibm_emac_core.o ibm_emac_phy.o 
+ibm_emac-$(CONFIG_IBM_EMAC_ZMII) += ibm_emac_zmii.o
+ibm_emac-$(CONFIG_IBM_EMAC_RGMII) += ibm_emac_rgmii.o
+ibm_emac-$(CONFIG_IBM_EMAC_TAH) += ibm_emac_tah.o
+ibm_emac-$(CONFIG_IBM_EMAC_DEBUG) += ibm_emac_debug.o
index 15d5a0e..28c476f 100644 (file)
 /*
- * ibm_emac.h
+ * drivers/net/ibm_emac/ibm_emac.h
  *
+ * Register definitions for PowerPC 4xx on-chip ethernet contoller
  *
- *      Armin Kuster akuster@mvista.com
- *      June, 2002
+ * Copyright (c) 2004, 2005 Zultys Technologies.
+ * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  *
- * Copyright 2002 MontaVista Softare Inc.
+ * Based on original work by
+ *      Matt Porter <mporter@kernel.crashing.org>
+ *      Armin Kuster <akuster@mvista.com>
+ *     Copyright 2002-2004 MontaVista Software Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
+ *
  */
+#ifndef __IBM_EMAC_H_
+#define __IBM_EMAC_H_
+
+#include <linux/config.h>
+#include <linux/types.h>
+
+/* This is a simple check to prevent use of this driver on non-tested SoCs */
+#if !defined(CONFIG_405GP) && !defined(CONFIG_405GPR) && !defined(CONFIG_405EP) && \
+    !defined(CONFIG_440GP) && !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && \
+    !defined(CONFIG_440EP) && !defined(CONFIG_NP405H)
+#error "Unknown SoC. Please, check chip user manual and make sure EMAC defines are OK"
+#endif
+
+/* EMAC registers              Write Access rules */
+struct emac_regs {
+       u32 mr0;                /* special      */
+       u32 mr1;                /* Reset        */
+       u32 tmr0;               /* special      */
+       u32 tmr1;               /* special      */
+       u32 rmr;                /* Reset        */
+       u32 isr;                /* Always       */
+       u32 iser;               /* Reset        */
+       u32 iahr;               /* Reset, R, T  */
+       u32 ialr;               /* Reset, R, T  */
+       u32 vtpid;              /* Reset, R, T  */
+       u32 vtci;               /* Reset, R, T  */
+       u32 ptr;                /* Reset,    T  */
+       u32 iaht1;              /* Reset, R     */
+       u32 iaht2;              /* Reset, R     */
+       u32 iaht3;              /* Reset, R     */
+       u32 iaht4;              /* Reset, R     */
+       u32 gaht1;              /* Reset, R     */
+       u32 gaht2;              /* Reset, R     */
+       u32 gaht3;              /* Reset, R     */
+       u32 gaht4;              /* Reset, R     */
+       u32 lsah;
+       u32 lsal;
+       u32 ipgvr;              /* Reset,    T  */
+       u32 stacr;              /* special      */
+       u32 trtr;               /* special      */
+       u32 rwmr;               /* Reset        */
+       u32 octx;
+       u32 ocrx;
+       u32 ipcr;
+};
+
+#if !defined(CONFIG_IBM_EMAC4)
+#define EMAC_ETHTOOL_REGS_VER          0
+#define EMAC_ETHTOOL_REGS_SIZE         (sizeof(struct emac_regs) - sizeof(u32))
+#else
+#define EMAC_ETHTOOL_REGS_VER          1
+#define EMAC_ETHTOOL_REGS_SIZE         sizeof(struct emac_regs)
+#endif
 
-#ifndef _IBM_EMAC_H_
-#define _IBM_EMAC_H_
-/* General defines needed for the driver */
+/* EMACx_MR0 */
+#define EMAC_MR0_RXI                   0x80000000
+#define EMAC_MR0_TXI                   0x40000000
+#define EMAC_MR0_SRST                  0x20000000
+#define EMAC_MR0_TXE                   0x10000000
+#define EMAC_MR0_RXE                   0x08000000
+#define EMAC_MR0_WKE                   0x04000000
 
-/* Emac */
-typedef struct emac_regs {
-       u32 em0mr0;
-       u32 em0mr1;
-       u32 em0tmr0;
-       u32 em0tmr1;
-       u32 em0rmr;
-       u32 em0isr;
-       u32 em0iser;
-       u32 em0iahr;
-       u32 em0ialr;
-       u32 em0vtpid;
-       u32 em0vtci;
-       u32 em0ptr;
-       u32 em0iaht1;
-       u32 em0iaht2;
-       u32 em0iaht3;
-       u32 em0iaht4;
-       u32 em0gaht1;
-       u32 em0gaht2;
-       u32 em0gaht3;
-       u32 em0gaht4;
-       u32 em0lsah;
-       u32 em0lsal;
-       u32 em0ipgvr;
-       u32 em0stacr;
-       u32 em0trtr;
-       u32 em0rwmr;
-} emac_t;
+/* EMACx_MR1 */
+#define EMAC_MR1_FDE                   0x80000000
+#define EMAC_MR1_ILE                   0x40000000
+#define EMAC_MR1_VLE                   0x20000000
+#define EMAC_MR1_EIFC                  0x10000000
+#define EMAC_MR1_APP                   0x08000000
+#define EMAC_MR1_IST                   0x01000000
 
-/* MODE REG 0 */
-#define EMAC_M0_RXI                    0x80000000
-#define EMAC_M0_TXI                    0x40000000
-#define EMAC_M0_SRST                   0x20000000
-#define EMAC_M0_TXE                    0x10000000
-#define EMAC_M0_RXE                    0x08000000
-#define EMAC_M0_WKE                    0x04000000
+#define EMAC_MR1_MF_MASK               0x00c00000
+#define EMAC_MR1_MF_10                 0x00000000
+#define EMAC_MR1_MF_100                        0x00400000
+#if !defined(CONFIG_IBM_EMAC4)
+#define EMAC_MR1_MF_1000               0x00000000
+#define EMAC_MR1_MF_1000GPCS           0x00000000
+#define EMAC_MR1_MF_IPPA(id)           0x00000000
+#else
+#define EMAC_MR1_MF_1000               0x00800000
+#define EMAC_MR1_MF_1000GPCS           0x00c00000
+#define EMAC_MR1_MF_IPPA(id)           (((id) & 0x1f) << 6)
+#endif
 
-/* MODE Reg 1 */
-#define EMAC_M1_FDE                    0x80000000
-#define EMAC_M1_ILE                    0x40000000
-#define EMAC_M1_VLE                    0x20000000
-#define EMAC_M1_EIFC                   0x10000000
-#define EMAC_M1_APP                    0x08000000
-#define EMAC_M1_AEMI                   0x02000000
-#define EMAC_M1_IST                    0x01000000
-#define EMAC_M1_MF_1000GPCS            0x00c00000      /* Internal GPCS */
-#define EMAC_M1_MF_1000MBPS            0x00800000      /* External GPCS */
-#define EMAC_M1_MF_100MBPS             0x00400000
-#define EMAC_M1_RFS_16K                 0x00280000     /* 000 for 512 byte */
-#define EMAC_M1_TR                     0x00008000
-#ifdef CONFIG_IBM_EMAC4
-#define EMAC_M1_RFS_8K                  0x00200000
-#define EMAC_M1_RFS_4K                  0x00180000
-#define EMAC_M1_RFS_2K                  0x00100000
-#define EMAC_M1_RFS_1K                  0x00080000
-#define EMAC_M1_TX_FIFO_16K             0x00050000     /* 0's for 512 byte */
-#define EMAC_M1_TX_FIFO_8K              0x00040000
-#define EMAC_M1_TX_FIFO_4K              0x00030000
-#define EMAC_M1_TX_FIFO_2K              0x00020000
-#define EMAC_M1_TX_FIFO_1K              0x00010000
-#define EMAC_M1_TX_TR                   0x00008000
-#define EMAC_M1_TX_MWSW                 0x00001000     /* 0 wait for status */
-#define EMAC_M1_JUMBO_ENABLE            0x00000800     /* Upt to 9Kr status */
-#define EMAC_M1_OPB_CLK_66              0x00000008     /* 66Mhz */
-#define EMAC_M1_OPB_CLK_83              0x00000010     /* 83Mhz */
-#define EMAC_M1_OPB_CLK_100             0x00000018     /* 100Mhz */
-#define EMAC_M1_OPB_CLK_100P            0x00000020     /* 100Mhz+ */
-#else                          /* CONFIG_IBM_EMAC4 */
-#define EMAC_M1_RFS_4K                 0x00300000      /* ~4k for 512 byte */
-#define EMAC_M1_RFS_2K                 0x00200000
-#define EMAC_M1_RFS_1K                 0x00100000
-#define EMAC_M1_TX_FIFO_2K             0x00080000      /* 0's for 512 byte */
-#define EMAC_M1_TX_FIFO_1K             0x00040000
-#define EMAC_M1_TR0_DEPEND             0x00010000      /* 0'x for single packet */
-#define EMAC_M1_TR1_DEPEND             0x00004000
-#define EMAC_M1_TR1_MULTI              0x00002000
-#define EMAC_M1_JUMBO_ENABLE           0x00001000
-#endif                         /* CONFIG_IBM_EMAC4 */
-#define EMAC_M1_BASE                   (EMAC_M1_TX_FIFO_2K | \
-                                       EMAC_M1_APP | \
-                                       EMAC_M1_TR | EMAC_M1_VLE)
+#define EMAC_TX_FIFO_SIZE              2048
 
-/* Transmit Mode Register 0 */
-#define EMAC_TMR0_GNP0                 0x80000000
-#define EMAC_TMR0_GNP1                 0x40000000
-#define EMAC_TMR0_GNPD                 0x20000000
-#define EMAC_TMR0_FC                   0x10000000
+#if !defined(CONFIG_IBM_EMAC4)
+#define EMAC_MR1_RFS_4K                        0x00300000
+#define EMAC_MR1_RFS_16K               0x00000000
+#define EMAC_RX_FIFO_SIZE(gige)                4096
+#define EMAC_MR1_TFS_2K                        0x00080000
+#define EMAC_MR1_TR0_MULT              0x00008000
+#define EMAC_MR1_JPSM                  0x00000000
+#define EMAC_MR1_BASE(opb)             (EMAC_MR1_TFS_2K | EMAC_MR1_TR0_MULT)
+#else
+#define EMAC_MR1_RFS_4K                        0x00180000
+#define EMAC_MR1_RFS_16K               0x00280000
+#define EMAC_RX_FIFO_SIZE(gige)                ((gige) ? 16384 : 4096)
+#define EMAC_MR1_TFS_2K                        0x00020000
+#define EMAC_MR1_TR                    0x00008000
+#define EMAC_MR1_MWSW_001              0x00001000
+#define EMAC_MR1_JPSM                  0x00000800
+#define EMAC_MR1_OBCI_MASK             0x00000038
+#define EMAC_MR1_OBCI_50               0x00000000
+#define EMAC_MR1_OBCI_66               0x00000008
+#define EMAC_MR1_OBCI_83               0x00000010
+#define EMAC_MR1_OBCI_100              0x00000018
+#define EMAC_MR1_OBCI_100P             0x00000020
+#define EMAC_MR1_OBCI(freq)            ((freq) <= 50  ? EMAC_MR1_OBCI_50 : \
+                                        (freq) <= 66  ? EMAC_MR1_OBCI_66 : \
+                                        (freq) <= 83  ? EMAC_MR1_OBCI_83 : \
+                                        (freq) <= 100 ? EMAC_MR1_OBCI_100 : EMAC_MR1_OBCI_100P)
+#define EMAC_MR1_BASE(opb)             (EMAC_MR1_TFS_2K | EMAC_MR1_TR | \
+                                        EMAC_MR1_MWSW_001 | EMAC_MR1_OBCI(opb))
+#endif
+
+/* EMACx_TMR0 */
+#define EMAC_TMR0_GNP                  0x80000000
+#if !defined(CONFIG_IBM_EMAC4)
+#define EMAC_TMR0_DEFAULT              0x00000000      
+#else
 #define EMAC_TMR0_TFAE_2_32            0x00000001
 #define EMAC_TMR0_TFAE_4_64            0x00000002
 #define EMAC_TMR0_TFAE_8_128           0x00000003
@@ -112,14 +144,36 @@ typedef struct emac_regs {
 #define EMAC_TMR0_TFAE_32_512          0x00000005
 #define EMAC_TMR0_TFAE_64_1024         0x00000006
 #define EMAC_TMR0_TFAE_128_2048                0x00000007
+#define EMAC_TMR0_DEFAULT              EMAC_TMR0_TFAE_2_32
+#endif
+#define EMAC_TMR0_XMIT                 (EMAC_TMR0_GNP | EMAC_TMR0_DEFAULT)
+
+/* EMACx_TMR1 */
+
+/* IBM manuals are not very clear here. 
+ * This is my interpretation of how things are. --ebs
+ */
+#if defined(CONFIG_40x)
+#define EMAC_FIFO_ENTRY_SIZE           8
+#define EMAC_MAL_BURST_SIZE            (16 * 4)
+#else
+#define EMAC_FIFO_ENTRY_SIZE           16
+#define EMAC_MAL_BURST_SIZE            (64 * 4)
+#endif
+
+#if !defined(CONFIG_IBM_EMAC4)
+#define EMAC_TMR1(l,h)                 (((l) << 27) | (((h) & 0xff) << 16))
+#else
+#define EMAC_TMR1(l,h)                 (((l) << 27) | (((h) & 0x3ff) << 14))
+#endif
 
-/* Receive Mode Register */
+/* EMACx_RMR */
 #define EMAC_RMR_SP                    0x80000000
 #define EMAC_RMR_SFCS                  0x40000000
-#define EMAC_RMR_ARRP                  0x20000000
-#define EMAC_RMR_ARP                   0x10000000
-#define EMAC_RMR_AROP                  0x08000000
-#define EMAC_RMR_ARPI                  0x04000000
+#define EMAC_RMR_RRP                   0x20000000
+#define EMAC_RMR_RFP                   0x10000000
+#define EMAC_RMR_ROP                   0x08000000
+#define EMAC_RMR_RPIR                  0x04000000
 #define EMAC_RMR_PPP                   0x02000000
 #define EMAC_RMR_PME                   0x01000000
 #define EMAC_RMR_PMME                  0x00800000
@@ -127,6 +181,9 @@ typedef struct emac_regs {
 #define EMAC_RMR_MIAE                  0x00200000
 #define EMAC_RMR_BAE                   0x00100000
 #define EMAC_RMR_MAE                   0x00080000
+#if !defined(CONFIG_IBM_EMAC4)
+#define EMAC_RMR_BASE                  0x00000000
+#else
 #define EMAC_RMR_RFAF_2_32             0x00000001
 #define EMAC_RMR_RFAF_4_64             0x00000002
 #define EMAC_RMR_RFAF_8_128            0x00000003
@@ -134,9 +191,21 @@ typedef struct emac_regs {
 #define EMAC_RMR_RFAF_32_512           0x00000005
 #define EMAC_RMR_RFAF_64_1024          0x00000006
 #define EMAC_RMR_RFAF_128_2048         0x00000007
-#define EMAC_RMR_BASE                  (EMAC_RMR_IAE | EMAC_RMR_BAE)
+#define EMAC_RMR_BASE                  EMAC_RMR_RFAF_128_2048
+#endif
 
-/* Interrupt Status & enable Regs */
+/* EMACx_ISR & EMACx_ISER */
+#if !defined(CONFIG_IBM_EMAC4)
+#define EMAC_ISR_TXPE                  0x00000000
+#define EMAC_ISR_RXPE                  0x00000000
+#define EMAC_ISR_TXUE                  0x00000000
+#define EMAC_ISR_RXOE                  0x00000000
+#else
+#define EMAC_ISR_TXPE                  0x20000000
+#define EMAC_ISR_RXPE                  0x10000000
+#define EMAC_ISR_TXUE                  0x08000000
+#define EMAC_ISR_RXOE                  0x04000000
+#endif
 #define EMAC_ISR_OVR                   0x02000000
 #define EMAC_ISR_PP                    0x01000000
 #define EMAC_ISR_BP                    0x00800000
@@ -147,53 +216,62 @@ typedef struct emac_regs {
 #define EMAC_ISR_PTLE                  0x00040000
 #define EMAC_ISR_ORE                   0x00020000
 #define EMAC_ISR_IRE                   0x00010000
-#define EMAC_ISR_DBDM                  0x00000200
-#define EMAC_ISR_DB0                   0x00000100
-#define EMAC_ISR_SE0                   0x00000080
-#define EMAC_ISR_TE0                   0x00000040
-#define EMAC_ISR_DB1                   0x00000020
-#define EMAC_ISR_SE1                   0x00000010
-#define EMAC_ISR_TE1                   0x00000008
+#define EMAC_ISR_SQE                   0x00000080
+#define EMAC_ISR_TE                    0x00000040
 #define EMAC_ISR_MOS                   0x00000002
 #define EMAC_ISR_MOF                   0x00000001
 
-/* STA CONTROL REG */
+/* EMACx_STACR */
+#define EMAC_STACR_PHYD_MASK           0xffff
+#define EMAC_STACR_PHYD_SHIFT          16
 #define EMAC_STACR_OC                  0x00008000
 #define EMAC_STACR_PHYE                        0x00004000
-#define EMAC_STACR_WRITE               0x00002000
-#define EMAC_STACR_READ                        0x00001000
-#define EMAC_STACR_CLK_83MHZ           0x00000800      /* 0's for 50Mhz */
-#define EMAC_STACR_CLK_66MHZ           0x00000400
-#define EMAC_STACR_CLK_100MHZ          0x00000C00
+#define EMAC_STACR_STAC_MASK           0x00003000
+#define EMAC_STACR_STAC_READ           0x00001000
+#define EMAC_STACR_STAC_WRITE          0x00002000
+#if !defined(CONFIG_IBM_EMAC4)
+#define EMAC_STACR_OPBC_MASK           0x00000C00
+#define EMAC_STACR_OPBC_50             0x00000000
+#define EMAC_STACR_OPBC_66             0x00000400
+#define EMAC_STACR_OPBC_83             0x00000800
+#define EMAC_STACR_OPBC_100            0x00000C00
+#define EMAC_STACR_OPBC(freq)          ((freq) <= 50 ? EMAC_STACR_OPBC_50 : \
+                                        (freq) <= 66 ? EMAC_STACR_OPBC_66 : \
+                                        (freq) <= 83 ? EMAC_STACR_OPBC_83 : EMAC_STACR_OPBC_100)
+#define EMAC_STACR_BASE(opb)           EMAC_STACR_OPBC(opb)
+#else
+#define EMAC_STACR_BASE(opb)           0x00000000
+#endif
+#define EMAC_STACR_PCDA_MASK           0x1f
+#define EMAC_STACR_PCDA_SHIFT          5
+#define EMAC_STACR_PRA_MASK            0x1f
+
+/* EMACx_TRTR */
+#if !defined(CONFIG_IBM_EMAC4)
+#define EMAC_TRTR_SHIFT                        27
+#else
+#define EMAC_TRTR_SHIFT                        24
+#endif
+#define EMAC_TRTR(size)                        ((((size) >> 6) - 1) << EMAC_TRTR_SHIFT)
 
-/* Transmit Request Threshold Register */
-#define EMAC_TRTR_1600                 0x18000000      /* 0's for 64 Bytes */
-#define EMAC_TRTR_1024                 0x0f000000
-#define EMAC_TRTR_512                  0x07000000
-#define EMAC_TRTR_256                  0x03000000
-#define EMAC_TRTR_192                  0x10000000
-#define EMAC_TRTR_128                  0x01000000
+/* EMACx_RWMR */
+#if !defined(CONFIG_IBM_EMAC4)
+#define EMAC_RWMR(l,h)                 (((l) << 23) | ( ((h) & 0x1ff) << 7))   
+#else
+#define EMAC_RWMR(l,h)                 (((l) << 22) | ( ((h) & 0x3ff) << 6))   
+#endif
 
+/* EMAC specific TX descriptor control fields (write access) */
 #define EMAC_TX_CTRL_GFCS              0x0200
 #define EMAC_TX_CTRL_GP                        0x0100
 #define EMAC_TX_CTRL_ISA               0x0080
 #define EMAC_TX_CTRL_RSA               0x0040
 #define EMAC_TX_CTRL_IVT               0x0020
 #define EMAC_TX_CTRL_RVT               0x0010
-#define EMAC_TX_CTRL_TAH_CSUM          0x000e  /* TAH only */
-#define EMAC_TX_CTRL_TAH_SEG4          0x000a  /* TAH only */
-#define EMAC_TX_CTRL_TAH_SEG3          0x0008  /* TAH only */
-#define EMAC_TX_CTRL_TAH_SEG2          0x0006  /* TAH only */
-#define EMAC_TX_CTRL_TAH_SEG1          0x0004  /* TAH only */
-#define EMAC_TX_CTRL_TAH_SEG0          0x0002  /* TAH only */
-#define EMAC_TX_CTRL_TAH_DIS           0x0000  /* TAH only */
+#define EMAC_TX_CTRL_TAH_CSUM          0x000e
 
-#define EMAC_TX_CTRL_DFLT ( \
-       MAL_TX_CTRL_INTR | EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP )
-
-/* madmal transmit status / Control bits */
+/* EMAC specific TX descriptor status fields (read access) */
 #define EMAC_TX_ST_BFCS                        0x0200
-#define EMAC_TX_ST_BPP                 0x0100
 #define EMAC_TX_ST_LCS                 0x0080
 #define EMAC_TX_ST_ED                  0x0040
 #define EMAC_TX_ST_EC                  0x0020
@@ -202,8 +280,16 @@ typedef struct emac_regs {
 #define EMAC_TX_ST_SC                  0x0004
 #define EMAC_TX_ST_UR                  0x0002
 #define EMAC_TX_ST_SQE                 0x0001
+#if !defined(CONFIG_IBM_EMAC_TAH)
+#define EMAC_IS_BAD_TX(v)              ((v) & (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
+                                        EMAC_TX_ST_EC | EMAC_TX_ST_LC | \
+                                        EMAC_TX_ST_MC | EMAC_TX_ST_UR))
+#else
+#define EMAC_IS_BAD_TX(v)              ((v) & (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
+                                        EMAC_TX_ST_EC | EMAC_TX_ST_LC))
+#endif                                  
 
-/* madmal receive status / Control bits */
+/* EMAC specific RX descriptor status fields (read access) */
 #define EMAC_RX_ST_OE                  0x0200
 #define EMAC_RX_ST_PP                  0x0100
 #define EMAC_RX_ST_BP                  0x0080
@@ -214,54 +300,10 @@ typedef struct emac_regs {
 #define EMAC_RX_ST_PTL                 0x0004
 #define EMAC_RX_ST_ORE                 0x0002
 #define EMAC_RX_ST_IRE                 0x0001
-#define EMAC_BAD_RX_PACKET             0x02ff
-#define EMAC_CSUM_VER_ERROR            0x0003
-
-/* identify a bad rx packet dependent on emac features */
-#ifdef CONFIG_IBM_EMAC4
-#define EMAC_IS_BAD_RX_PACKET(desc) \
-       (((desc & (EMAC_BAD_RX_PACKET & ~EMAC_CSUM_VER_ERROR)) || \
-       ((desc & EMAC_CSUM_VER_ERROR) == EMAC_RX_ST_ORE) || \
-       ((desc & EMAC_CSUM_VER_ERROR) == EMAC_RX_ST_IRE)))
-#else
-#define EMAC_IS_BAD_RX_PACKET(desc) \
-        (desc & EMAC_BAD_RX_PACKET)
-#endif
-
-/* SoC implementation specific EMAC register defaults */
-#if defined(CONFIG_440GP)
-#define EMAC_RWMR_DEFAULT              0x80009000
-#define EMAC_TMR0_DEFAULT              0x00000000
-#define EMAC_TMR1_DEFAULT              0xf8640000
-#elif defined(CONFIG_440GX)
-#define EMAC_RWMR_DEFAULT              0x1000a200
-#define EMAC_TMR0_DEFAULT              EMAC_TMR0_TFAE_2_32
-#define EMAC_TMR1_DEFAULT              0xa00f0000
-#elif defined(CONFIG_440SP)
-#define EMAC_RWMR_DEFAULT              0x08002000
-#define EMAC_TMR0_DEFAULT              EMAC_TMR0_TFAE_128_2048
-#define EMAC_TMR1_DEFAULT              0xf8200000
-#else
-#define EMAC_RWMR_DEFAULT              0x0f002000
-#define EMAC_TMR0_DEFAULT              0x00000000
-#define EMAC_TMR1_DEFAULT              0x380f0000
-#endif                         /* CONFIG_440GP */
-
-/* Revision specific EMAC register defaults */
-#ifdef CONFIG_IBM_EMAC4
-#define EMAC_M1_DEFAULT                        (EMAC_M1_BASE | \
-                                       EMAC_M1_OPB_CLK_83 | \
-                                       EMAC_M1_TX_MWSW)
-#define EMAC_RMR_DEFAULT               (EMAC_RMR_BASE | \
-                                       EMAC_RMR_RFAF_128_2048)
-#define EMAC_TMR0_XMIT                 (EMAC_TMR0_GNP0 | \
-                                       EMAC_TMR0_DEFAULT)
-#define EMAC_TRTR_DEFAULT              EMAC_TRTR_1024
-#else                          /* !CONFIG_IBM_EMAC4 */
-#define EMAC_M1_DEFAULT                        EMAC_M1_BASE
-#define EMAC_RMR_DEFAULT               EMAC_RMR_BASE
-#define EMAC_TMR0_XMIT                 EMAC_TMR0_GNP0
-#define EMAC_TRTR_DEFAULT              EMAC_TRTR_1600
-#endif                         /* CONFIG_IBM_EMAC4 */
-
-#endif
+#define EMAC_RX_TAH_BAD_CSUM           0x0003
+#define EMAC_BAD_RX_MASK               (EMAC_RX_ST_OE | EMAC_RX_ST_BP | \
+                                        EMAC_RX_ST_RP | EMAC_RX_ST_SE | \
+                                        EMAC_RX_ST_AE | EMAC_RX_ST_BFCS | \
+                                        EMAC_RX_ST_PTL | EMAC_RX_ST_ORE | \
+                                        EMAC_RX_ST_IRE )
+#endif /* __IBM_EMAC_H_ */
index 14e9b63..943fbd1 100644 (file)
@@ -1,13 +1,14 @@
 /*
- * ibm_emac_core.c
+ * drivers/net/ibm_emac/ibm_emac_core.c
  *
- * Ethernet driver for the built in ethernet on the IBM 4xx PowerPC
- * processors.
- * 
- * (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
+ * Driver for PowerPC 4xx on-chip ethernet controller.
  *
- * Based on original work by
+ * Copyright (c) 2004, 2005 Zultys Technologies.
+ * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  *
+ * Based on original work by
+ *     Matt Porter <mporter@kernel.crashing.org>
+ *     (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
  *      Armin Kuster <akuster@mvista.com>
  *     Johnnie Peters <jpeters@mvista.com>
  *
  * under  the terms of  the GNU General  Public License as published by the
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
- * TODO
- *       - Check for races in the "remove" code path
- *       - Add some Power Management to the MAC and the PHY
- *       - Audit remaining of non-rewritten code (--BenH)
- *       - Cleanup message display using msglevel mecanism
- *       - Address all errata
- *       - Audit all register update paths to ensure they
- *         are being written post soft reset if required.
+ *
  */
+
+#include <linux/config.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/string.h>
-#include <linux/timer.h>
-#include <linux/ptrace.h>
 #include <linux/errno.h>
-#include <linux/ioport.h>
-#include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/types.h>
-#include <linux/dma-mapping.h>
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/crc32.h>
 #include <linux/ethtool.h>
 #include <linux/mii.h>
 #include <linux/bitops.h>
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/dma.h>
-#include <asm/irq.h>
 #include <asm/uaccess.h>
 #include <asm/ocp.h>
 
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/skbuff.h>
-#include <linux/crc32.h>
-
 #include "ibm_emac_core.h"
-
-//#define MDIO_DEBUG(fmt) printk fmt
-#define MDIO_DEBUG(fmt)
-
-//#define LINK_DEBUG(fmt) printk fmt
-#define LINK_DEBUG(fmt)
-
-//#define PKT_DEBUG(fmt) printk fmt
-#define PKT_DEBUG(fmt)
-
-#define DRV_NAME        "emac"
-#define DRV_VERSION     "2.0"
-#define DRV_AUTHOR      "Benjamin Herrenschmidt <benh@kernel.crashing.org>"
-#define DRV_DESC        "IBM EMAC Ethernet driver"
+#include "ibm_emac_debug.h"
 
 /*
- * When mdio_idx >= 0, contains a list of emac ocp_devs
- * that have had their initialization deferred until the
- * common MDIO controller has been initialized.
+ * Lack of dma_unmap_???? calls is intentional.
+ *
+ * API-correct usage requires additional support state information to be 
+ * maintained for every RX and TX buffer descriptor (BD). Unfortunately, due to
+ * EMAC design (e.g. TX buffer passed from network stack can be split into
+ * several BDs, dma_map_single/dma_map_page can be used to map particular BD),
+ * maintaining such information will add additional overhead.
+ * Current DMA API implementation for 4xx processors only ensures cache coherency
+ * and dma_unmap_???? routines are empty and are likely to stay this way.
+ * I decided to omit dma_unmap_??? calls because I don't want to add additional
+ * complexity just for the sake of following some abstract API, when it doesn't
+ * add any real benefit to the driver. I understand that this decision maybe 
+ * controversial, but I really tried to make code API-correct and efficient 
+ * at the same time and didn't come up with code I liked :(.                --ebs
  */
-LIST_HEAD(emac_init_list);
 
-MODULE_AUTHOR(DRV_AUTHOR);
+#define DRV_NAME        "emac"
+#define DRV_VERSION     "3.53"
+#define DRV_DESC        "PPC 4xx OCP EMAC driver"
+
 MODULE_DESCRIPTION(DRV_DESC);
+MODULE_AUTHOR
+    ("Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>");
 MODULE_LICENSE("GPL");
 
-static int skb_res = SKB_RES;
-module_param(skb_res, int, 0444);
-MODULE_PARM_DESC(skb_res, "Amount of data to reserve on skb buffs\n"
-                "The 405 handles a misaligned IP header fine but\n"
-                "this can help if you are routing to a tunnel or a\n"
-                "device that needs aligned data. 0..2");
-
-#define RGMII_PRIV(ocpdev) ((struct ibm_ocp_rgmii*)ocp_get_drvdata(ocpdev))
+/* minimum number of free TX descriptors required to wake up TX process */
+#define EMAC_TX_WAKEUP_THRESH          (NUM_TX_BUFF / 4)
 
-static unsigned int rgmii_enable[] = {
-       RGMII_RTBI,
-       RGMII_RGMII,
-       RGMII_TBI,
-       RGMII_GMII
-};
+/* If packet size is less than this number, we allocate small skb and copy packet 
+ * contents into it instead of just sending original big skb up
+ */
+#define EMAC_RX_COPY_THRESH            CONFIG_IBM_EMAC_RX_COPY_THRESHOLD
 
-static unsigned int rgmii_speed_mask[] = {
-       RGMII_MII2_SPDMASK,
-       RGMII_MII3_SPDMASK
-};
+/* Since multiple EMACs share MDIO lines in various ways, we need
+ * to avoid re-using the same PHY ID in cases where the arch didn't
+ * setup precise phy_map entries
+ */
+static u32 busy_phy_map;
 
-static unsigned int rgmii_speed100[] = {
-       RGMII_MII2_100MB,
-       RGMII_MII3_100MB
-};
+#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && (defined(CONFIG_405EP) || defined(CONFIG_440EP))
+/* 405EP has "EMAC to PHY Control Register" (CPC0_EPCTL) which can help us
+ * with PHY RX clock problem.
+ * 440EP has more sane SDR0_MFR register implementation than 440GX, which
+ * also allows controlling each EMAC clock
+ */
+static inline void EMAC_RX_CLK_TX(int idx)
+{
+       unsigned long flags;
+       local_irq_save(flags);
 
-static unsigned int rgmii_speed1000[] = {
-       RGMII_MII2_1000MB,
-       RGMII_MII3_1000MB
-};
+#if defined(CONFIG_405EP)
+       mtdcr(0xf3, mfdcr(0xf3) | (1 << idx));
+#else /* CONFIG_440EP */
+       SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) | (0x08000000 >> idx));
+#endif
 
-#define ZMII_PRIV(ocpdev) ((struct ibm_ocp_zmii*)ocp_get_drvdata(ocpdev))
+       local_irq_restore(flags);
+}
 
-static unsigned int zmii_enable[][4] = {
-       {ZMII_SMII0, ZMII_RMII0, ZMII_MII0,
-        ~(ZMII_MDI1 | ZMII_MDI2 | ZMII_MDI3)},
-       {ZMII_SMII1, ZMII_RMII1, ZMII_MII1,
-        ~(ZMII_MDI0 | ZMII_MDI2 | ZMII_MDI3)},
-       {ZMII_SMII2, ZMII_RMII2, ZMII_MII2,
-        ~(ZMII_MDI0 | ZMII_MDI1 | ZMII_MDI3)},
-       {ZMII_SMII3, ZMII_RMII3, ZMII_MII3, ~(ZMII_MDI0 | ZMII_MDI1 | ZMII_MDI2)}
-};
+static inline void EMAC_RX_CLK_DEFAULT(int idx)
+{
+       unsigned long flags;
+       local_irq_save(flags);
 
-static unsigned int mdi_enable[] = {
-       ZMII_MDI0,
-       ZMII_MDI1,
-       ZMII_MDI2,
-       ZMII_MDI3
-};
+#if defined(CONFIG_405EP)
+       mtdcr(0xf3, mfdcr(0xf3) & ~(1 << idx));
+#else /* CONFIG_440EP */
+       SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) & ~(0x08000000 >> idx));
+#endif
 
-static unsigned int zmii_speed = 0x0;
-static unsigned int zmii_speed100[] = {
-       ZMII_MII0_100MB,
-       ZMII_MII1_100MB,
-       ZMII_MII2_100MB,
-       ZMII_MII3_100MB
-};
+       local_irq_restore(flags);
+}
+#else
+#define EMAC_RX_CLK_TX(idx)            ((void)0)
+#define EMAC_RX_CLK_DEFAULT(idx)       ((void)0)
+#endif
 
-/* Since multiple EMACs share MDIO lines in various ways, we need
- * to avoid re-using the same PHY ID in cases where the arch didn't
- * setup precise phy_map entries
+#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX) && defined(CONFIG_440GX)
+/* We can switch Ethernet clock to the internal source through SDR0_MFR[ECS],
+ * unfortunately this is less flexible than 440EP case, because it's a global 
+ * setting for all EMACs, therefore we do this clock trick only during probe.
  */
-static u32 busy_phy_map = 0;
+#define EMAC_CLK_INTERNAL              SDR_WRITE(DCRN_SDR_MFR, \
+                                           SDR_READ(DCRN_SDR_MFR) | 0x08000000)
+#define EMAC_CLK_EXTERNAL              SDR_WRITE(DCRN_SDR_MFR, \
+                                           SDR_READ(DCRN_SDR_MFR) & ~0x08000000)
+#else
+#define EMAC_CLK_INTERNAL              ((void)0)
+#define EMAC_CLK_EXTERNAL              ((void)0)
+#endif
 
-/* If EMACs share a common MDIO device, this points to it */
-static struct net_device *mdio_ndev = NULL;
+/* I don't want to litter system log with timeout errors 
+ * when we have brain-damaged PHY.
+ */
+static inline void emac_report_timeout_error(struct ocp_enet_private *dev,
+                                            const char *error)
+{
+#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX)
+       DBG("%d: %s" NL, dev->def->index, error);
+#else
+       if (net_ratelimit())
+               printk(KERN_ERR "emac%d: %s\n", dev->def->index, error);
+#endif
+}
 
-struct emac_def_dev {
-       struct list_head link;
-       struct ocp_device *ocpdev;
-       struct ibm_ocp_mal *mal;
+/* PHY polling intervals */
+#define PHY_POLL_LINK_ON       HZ
+#define PHY_POLL_LINK_OFF      (HZ / 5)
+
+/* Please, keep in sync with struct ibm_emac_stats/ibm_emac_error_stats */
+static const char emac_stats_keys[EMAC_ETHTOOL_STATS_COUNT][ETH_GSTRING_LEN] = {
+       "rx_packets", "rx_bytes", "tx_packets", "tx_bytes", "rx_packets_csum",
+       "tx_packets_csum", "tx_undo", "rx_dropped_stack", "rx_dropped_oom",
+       "rx_dropped_error", "rx_dropped_resize", "rx_dropped_mtu",
+       "rx_stopped", "rx_bd_errors", "rx_bd_overrun", "rx_bd_bad_packet",
+       "rx_bd_runt_packet", "rx_bd_short_event", "rx_bd_alignment_error",
+       "rx_bd_bad_fcs", "rx_bd_packet_too_long", "rx_bd_out_of_range",
+       "rx_bd_in_range", "rx_parity", "rx_fifo_overrun", "rx_overrun",
+       "rx_bad_packet", "rx_runt_packet", "rx_short_event",
+       "rx_alignment_error", "rx_bad_fcs", "rx_packet_too_long",
+       "rx_out_of_range", "rx_in_range", "tx_dropped", "tx_bd_errors",
+       "tx_bd_bad_fcs", "tx_bd_carrier_loss", "tx_bd_excessive_deferral",
+       "tx_bd_excessive_collisions", "tx_bd_late_collision",
+       "tx_bd_multple_collisions", "tx_bd_single_collision",
+       "tx_bd_underrun", "tx_bd_sqe", "tx_parity", "tx_underrun", "tx_sqe",
+       "tx_errors"
 };
 
-static struct net_device_stats *emac_stats(struct net_device *dev)
+static irqreturn_t emac_irq(int irq, void *dev_instance, struct pt_regs *regs);
+static void emac_clean_tx_ring(struct ocp_enet_private *dev);
+
+static inline int emac_phy_supports_gige(int phy_mode)
 {
-       struct ocp_enet_private *fep = dev->priv;
-       return &fep->stats;
-};
+       return  phy_mode == PHY_MODE_GMII ||
+               phy_mode == PHY_MODE_RGMII ||
+               phy_mode == PHY_MODE_TBI ||
+               phy_mode == PHY_MODE_RTBI;
+}
 
-static int
-emac_init_rgmii(struct ocp_device *rgmii_dev, int input, int phy_mode)
+static inline int emac_phy_gpcs(int phy_mode)
 {
-       struct ibm_ocp_rgmii *rgmii = RGMII_PRIV(rgmii_dev);
-       const char *mode_name[] = { "RTBI", "RGMII", "TBI", "GMII" };
-       int mode = -1;
+       return  phy_mode == PHY_MODE_TBI ||
+               phy_mode == PHY_MODE_RTBI;
+}
 
-       if (!rgmii) {
-               rgmii = kmalloc(sizeof(struct ibm_ocp_rgmii), GFP_KERNEL);
+static inline void emac_tx_enable(struct ocp_enet_private *dev)
+{
+       struct emac_regs *p = dev->emacp;
+       unsigned long flags;
+       u32 r;
 
-               if (rgmii == NULL) {
-                       printk(KERN_ERR
-                              "rgmii%d: Out of memory allocating RGMII structure!\n",
-                              rgmii_dev->def->index);
-                       return -ENOMEM;
-               }
+       local_irq_save(flags);
 
-               memset(rgmii, 0, sizeof(*rgmii));
+       DBG("%d: tx_enable" NL, dev->def->index);
 
-               rgmii->base =
-                   (struct rgmii_regs *)ioremap(rgmii_dev->def->paddr,
-                                                sizeof(*rgmii->base));
-               if (rgmii->base == NULL) {
-                       printk(KERN_ERR
-                              "rgmii%d: Cannot ioremap bridge registers!\n",
-                              rgmii_dev->def->index);
+       r = in_be32(&p->mr0);
+       if (!(r & EMAC_MR0_TXE))
+               out_be32(&p->mr0, r | EMAC_MR0_TXE);
+       local_irq_restore(flags);
+}
 
-                       kfree(rgmii);
-                       return -ENOMEM;
-               }
-               ocp_set_drvdata(rgmii_dev, rgmii);
-       }
+static void emac_tx_disable(struct ocp_enet_private *dev)
+{
+       struct emac_regs *p = dev->emacp;
+       unsigned long flags;
+       u32 r;
 
-       if (phy_mode) {
-               switch (phy_mode) {
-               case PHY_MODE_GMII:
-                       mode = GMII;
-                       break;
-               case PHY_MODE_TBI:
-                       mode = TBI;
-                       break;
-               case PHY_MODE_RTBI:
-                       mode = RTBI;
-                       break;
-               case PHY_MODE_RGMII:
-               default:
-                       mode = RGMII;
-               }
-               rgmii->base->fer &= ~RGMII_FER_MASK(input);
-               rgmii->base->fer |= rgmii_enable[mode] << (4 * input);
-       } else {
-               switch ((rgmii->base->fer & RGMII_FER_MASK(input)) >> (4 *
-                                                                      input)) {
-               case RGMII_RTBI:
-                       mode = RTBI;
-                       break;
-               case RGMII_RGMII:
-                       mode = RGMII;
-                       break;
-               case RGMII_TBI:
-                       mode = TBI;
-                       break;
-               case RGMII_GMII:
-                       mode = GMII;
-               }
-       }
+       local_irq_save(flags);
+
+       DBG("%d: tx_disable" NL, dev->def->index);
 
-       /* Set mode to RGMII if nothing valid is detected */
-       if (mode < 0)
-               mode = RGMII;
+       r = in_be32(&p->mr0);
+       if (r & EMAC_MR0_TXE) {
+               int n = 300;
+               out_be32(&p->mr0, r & ~EMAC_MR0_TXE);
+               while (!(in_be32(&p->mr0) & EMAC_MR0_TXI) && n)
+                       --n;
+               if (unlikely(!n))
+                       emac_report_timeout_error(dev, "TX disable timeout");
+       }
+       local_irq_restore(flags);
+}
 
-       printk(KERN_NOTICE "rgmii%d: input %d in %s mode\n",
-              rgmii_dev->def->index, input, mode_name[mode]);
+static void emac_rx_enable(struct ocp_enet_private *dev)
+{
+       struct emac_regs *p = dev->emacp;
+       unsigned long flags;
+       u32 r;
 
-       rgmii->mode[input] = mode;
-       rgmii->users++;
+       local_irq_save(flags);
+       if (unlikely(dev->commac.rx_stopped))
+               goto out;
 
-       return 0;
+       DBG("%d: rx_enable" NL, dev->def->index);
+
+       r = in_be32(&p->mr0);
+       if (!(r & EMAC_MR0_RXE)) {
+               if (unlikely(!(r & EMAC_MR0_RXI))) {
+                       /* Wait if previous async disable is still in progress */
+                       int n = 100;
+                       while (!(r = in_be32(&p->mr0) & EMAC_MR0_RXI) && n)
+                               --n;
+                       if (unlikely(!n))
+                               emac_report_timeout_error(dev,
+                                                         "RX disable timeout");
+               }
+               out_be32(&p->mr0, r | EMAC_MR0_RXE);
+       }
+      out:
+       local_irq_restore(flags);
 }
 
-static void
-emac_rgmii_port_speed(struct ocp_device *ocpdev, int input, int speed)
+static void emac_rx_disable(struct ocp_enet_private *dev)
 {
-       struct ibm_ocp_rgmii *rgmii = RGMII_PRIV(ocpdev);
-       unsigned int rgmii_speed;
-
-       rgmii_speed = in_be32(&rgmii->base->ssr);
+       struct emac_regs *p = dev->emacp;
+       unsigned long flags;
+       u32 r;
 
-       rgmii_speed &= ~rgmii_speed_mask[input];
+       local_irq_save(flags);
 
-       if (speed == 1000)
-               rgmii_speed |= rgmii_speed1000[input];
-       else if (speed == 100)
-               rgmii_speed |= rgmii_speed100[input];
+       DBG("%d: rx_disable" NL, dev->def->index);
 
-       out_be32(&rgmii->base->ssr, rgmii_speed);
+       r = in_be32(&p->mr0);
+       if (r & EMAC_MR0_RXE) {
+               int n = 300;
+               out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
+               while (!(in_be32(&p->mr0) & EMAC_MR0_RXI) && n)
+                       --n;
+               if (unlikely(!n))
+                       emac_report_timeout_error(dev, "RX disable timeout");
+       }
+       local_irq_restore(flags);
 }
 
-static void emac_close_rgmii(struct ocp_device *ocpdev)
+static inline void emac_rx_disable_async(struct ocp_enet_private *dev)
 {
-       struct ibm_ocp_rgmii *rgmii = RGMII_PRIV(ocpdev);
-       BUG_ON(!rgmii || rgmii->users == 0);
+       struct emac_regs *p = dev->emacp;
+       unsigned long flags;
+       u32 r;
 
-       if (!--rgmii->users) {
-               ocp_set_drvdata(ocpdev, NULL);
-               iounmap((void *)rgmii->base);
-               kfree(rgmii);
-       }
+       local_irq_save(flags);
+
+       DBG("%d: rx_disable_async" NL, dev->def->index);
+
+       r = in_be32(&p->mr0);
+       if (r & EMAC_MR0_RXE)
+               out_be32(&p->mr0, r & ~EMAC_MR0_RXE);
+       local_irq_restore(flags);
 }
 
-static int emac_init_zmii(struct ocp_device *zmii_dev, int input, int phy_mode)
+static int emac_reset(struct ocp_enet_private *dev)
 {
-       struct ibm_ocp_zmii *zmii = ZMII_PRIV(zmii_dev);
-       const char *mode_name[] = { "SMII", "RMII", "MII" };
-       int mode = -1;
+       struct emac_regs *p = dev->emacp;
+       unsigned long flags;
+       int n = 20;
 
-       if (!zmii) {
-               zmii = kmalloc(sizeof(struct ibm_ocp_zmii), GFP_KERNEL);
-               if (zmii == NULL) {
-                       printk(KERN_ERR
-                              "zmii%d: Out of memory allocating ZMII structure!\n",
-                              zmii_dev->def->index);
-                       return -ENOMEM;
-               }
-               memset(zmii, 0, sizeof(*zmii));
+       DBG("%d: reset" NL, dev->def->index);
 
-               zmii->base =
-                   (struct zmii_regs *)ioremap(zmii_dev->def->paddr,
-                                               sizeof(*zmii->base));
-               if (zmii->base == NULL) {
-                       printk(KERN_ERR
-                              "zmii%d: Cannot ioremap bridge registers!\n",
-                              zmii_dev->def->index);
+       local_irq_save(flags);
 
-                       kfree(zmii);
-                       return -ENOMEM;
-               }
-               ocp_set_drvdata(zmii_dev, zmii);
+       if (!dev->reset_failed) {
+               /* 40x erratum suggests stopping RX channel before reset,
+                * we stop TX as well
+                */
+               emac_rx_disable(dev);
+               emac_tx_disable(dev);
        }
 
-       if (phy_mode) {
-               switch (phy_mode) {
-               case PHY_MODE_MII:
-                       mode = MII;
-                       break;
-               case PHY_MODE_RMII:
-                       mode = RMII;
-                       break;
-               case PHY_MODE_SMII:
-               default:
-                       mode = SMII;
-               }
-               zmii->base->fer &= ~ZMII_FER_MASK(input);
-               zmii->base->fer |= zmii_enable[input][mode];
+       out_be32(&p->mr0, EMAC_MR0_SRST);
+       while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n)
+               --n;
+       local_irq_restore(flags);
+
+       if (n) {
+               dev->reset_failed = 0;
+               return 0;
        } else {
-               switch ((zmii->base->fer & ZMII_FER_MASK(input)) << (4 * input)) {
-               case ZMII_MII0:
-                       mode = MII;
-                       break;
-               case ZMII_RMII0:
-                       mode = RMII;
-                       break;
-               case ZMII_SMII0:
-                       mode = SMII;
-               }
+               emac_report_timeout_error(dev, "reset timeout");
+               dev->reset_failed = 1;
+               return -ETIMEDOUT;
        }
+}
 
-       /* Set mode to SMII if nothing valid is detected */
-       if (mode < 0)
-               mode = SMII;
+static void emac_hash_mc(struct ocp_enet_private *dev)
+{
+       struct emac_regs *p = dev->emacp;
+       u16 gaht[4] = { 0 };
+       struct dev_mc_list *dmi;
 
-       printk(KERN_NOTICE "zmii%d: input %d in %s mode\n",
-              zmii_dev->def->index, input, mode_name[mode]);
+       DBG("%d: hash_mc %d" NL, dev->def->index, dev->ndev->mc_count);
 
-       zmii->mode[input] = mode;
-       zmii->users++;
+       for (dmi = dev->ndev->mc_list; dmi; dmi = dmi->next) {
+               int bit;
+               DBG2("%d: mc %02x:%02x:%02x:%02x:%02x:%02x" NL,
+                    dev->def->index,
+                    dmi->dmi_addr[0], dmi->dmi_addr[1], dmi->dmi_addr[2],
+                    dmi->dmi_addr[3], dmi->dmi_addr[4], dmi->dmi_addr[5]);
 
-       return 0;
+               bit = 63 - (ether_crc(ETH_ALEN, dmi->dmi_addr) >> 26);
+               gaht[bit >> 4] |= 0x8000 >> (bit & 0x0f);
+       }
+       out_be32(&p->gaht1, gaht[0]);
+       out_be32(&p->gaht2, gaht[1]);
+       out_be32(&p->gaht3, gaht[2]);
+       out_be32(&p->gaht4, gaht[3]);
 }
 
-static void emac_enable_zmii_port(struct ocp_device *ocpdev, int input)
+static inline u32 emac_iff2rmr(struct net_device *ndev)
 {
-       u32 mask;
-       struct ibm_ocp_zmii *zmii = ZMII_PRIV(ocpdev);
+       u32 r = EMAC_RMR_SP | EMAC_RMR_SFCS | EMAC_RMR_IAE | EMAC_RMR_BAE |
+           EMAC_RMR_BASE;
 
-       mask = in_be32(&zmii->base->fer);
-       mask &= zmii_enable[input][MDI];        /* turn all non enabled MDI's off */
-       mask |= zmii_enable[input][zmii->mode[input]] | mdi_enable[input];
-       out_be32(&zmii->base->fer, mask);
+       if (ndev->flags & IFF_PROMISC)
+               r |= EMAC_RMR_PME;
+       else if (ndev->flags & IFF_ALLMULTI || ndev->mc_count > 32)
+               r |= EMAC_RMR_PMME;
+       else if (ndev->mc_count > 0)
+               r |= EMAC_RMR_MAE;
+
+       return r;
 }
 
-static void
-emac_zmii_port_speed(struct ocp_device *ocpdev, int input, int speed)
+static inline int emac_opb_mhz(void)
 {
-       struct ibm_ocp_zmii *zmii = ZMII_PRIV(ocpdev);
-
-       if (speed == 100)
-               zmii_speed |= zmii_speed100[input];
-       else
-               zmii_speed &= ~zmii_speed100[input];
-
-       out_be32(&zmii->base->ssr, zmii_speed);
+       return (ocp_sys_info.opb_bus_freq + 500000) / 1000000;
 }
 
-static void emac_close_zmii(struct ocp_device *ocpdev)
+/* BHs disabled */
+static int emac_configure(struct ocp_enet_private *dev)
 {
-       struct ibm_ocp_zmii *zmii = ZMII_PRIV(ocpdev);
-       BUG_ON(!zmii || zmii->users == 0);
+       struct emac_regs *p = dev->emacp;
+       struct net_device *ndev = dev->ndev;
+       int gige;
+       u32 r;
 
-       if (!--zmii->users) {
-               ocp_set_drvdata(ocpdev, NULL);
-               iounmap((void *)zmii->base);
-               kfree(zmii);
-       }
-}
+       DBG("%d: configure" NL, dev->def->index);
 
-int emac_phy_read(struct net_device *dev, int mii_id, int reg)
-{
-       int count;
-       uint32_t stacr;
-       struct ocp_enet_private *fep = dev->priv;
-       emac_t *emacp = fep->emacp;
+       if (emac_reset(dev) < 0)
+               return -ETIMEDOUT;
 
-       MDIO_DEBUG(("%s: phy_read, id: 0x%x, reg: 0x%x\n", dev->name, mii_id,
-                   reg));
+       tah_reset(dev->tah_dev);
 
-       /* Enable proper ZMII port */
-       if (fep->zmii_dev)
-               emac_enable_zmii_port(fep->zmii_dev, fep->zmii_input);
+       /* Mode register */
+       r = EMAC_MR1_BASE(emac_opb_mhz()) | EMAC_MR1_VLE | EMAC_MR1_IST;
+       if (dev->phy.duplex == DUPLEX_FULL)
+               r |= EMAC_MR1_FDE;
+       switch (dev->phy.speed) {
+       case SPEED_1000:
+               if (emac_phy_gpcs(dev->phy.mode)) {
+                       r |= EMAC_MR1_MF_1000GPCS |
+                           EMAC_MR1_MF_IPPA(dev->phy.address);
 
-       /* Use the EMAC that has the MDIO port */
-       if (fep->mdio_dev) {
-               dev = fep->mdio_dev;
-               fep = dev->priv;
-               emacp = fep->emacp;
+                       /* Put some arbitrary OUI, Manuf & Rev IDs so we can
+                        * identify this GPCS PHY later.
+                        */
+                       out_be32(&p->ipcr, 0xdeadbeef);
+               } else
+                       r |= EMAC_MR1_MF_1000;
+               r |= EMAC_MR1_RFS_16K;
+               gige = 1;
+               
+               if (dev->ndev->mtu > ETH_DATA_LEN)
+                       r |= EMAC_MR1_JPSM;
+               break;
+       case SPEED_100:
+               r |= EMAC_MR1_MF_100;
+               /* Fall through */
+       default:
+               r |= EMAC_MR1_RFS_4K;
+               gige = 0;
+               break;
        }
 
-       count = 0;
-       while ((((stacr = in_be32(&emacp->em0stacr)) & EMAC_STACR_OC) == 0)
-                                       && (count++ < MDIO_DELAY))
-               udelay(1);
-       MDIO_DEBUG((" (count was %d)\n", count));
+       if (dev->rgmii_dev)
+               rgmii_set_speed(dev->rgmii_dev, dev->rgmii_input,
+                               dev->phy.speed);
+       else
+               zmii_set_speed(dev->zmii_dev, dev->zmii_input, dev->phy.speed);
 
-       if ((stacr & EMAC_STACR_OC) == 0) {
-               printk(KERN_WARNING "%s: PHY read timeout #1!\n", dev->name);
-               return -1;
+#if !defined(CONFIG_40x)
+       /* on 40x erratum forces us to NOT use integrated flow control, 
+        * let's hope it works on 44x ;)
+        */
+       if (dev->phy.duplex == DUPLEX_FULL) {
+               if (dev->phy.pause)
+                       r |= EMAC_MR1_EIFC | EMAC_MR1_APP;
+               else if (dev->phy.asym_pause)
+                       r |= EMAC_MR1_APP;
        }
+#endif
+       out_be32(&p->mr1, r);
+
+       /* Set individual MAC address */
+       out_be32(&p->iahr, (ndev->dev_addr[0] << 8) | ndev->dev_addr[1]);
+       out_be32(&p->ialr, (ndev->dev_addr[2] << 24) |
+                (ndev->dev_addr[3] << 16) | (ndev->dev_addr[4] << 8) |
+                ndev->dev_addr[5]);
+
+       /* VLAN Tag Protocol ID */
+       out_be32(&p->vtpid, 0x8100);
+
+       /* Receive mode register */
+       r = emac_iff2rmr(ndev);
+       if (r & EMAC_RMR_MAE)
+               emac_hash_mc(dev);
+       out_be32(&p->rmr, r);
+
+       /* FIFOs thresholds */
+       r = EMAC_TMR1((EMAC_MAL_BURST_SIZE / EMAC_FIFO_ENTRY_SIZE) + 1,
+                     EMAC_TX_FIFO_SIZE / 2 / EMAC_FIFO_ENTRY_SIZE);
+       out_be32(&p->tmr1, r);
+       out_be32(&p->trtr, EMAC_TRTR(EMAC_TX_FIFO_SIZE / 2));
+
+       /* PAUSE frame is sent when RX FIFO reaches its high-water mark,
+          there should be still enough space in FIFO to allow the our link
+          partner time to process this frame and also time to send PAUSE 
+          frame itself.
+
+          Here is the worst case scenario for the RX FIFO "headroom"
+          (from "The Switch Book") (100Mbps, without preamble, inter-frame gap):
+
+          1) One maximum-length frame on TX                    1522 bytes
+          2) One PAUSE frame time                                64 bytes
+          3) PAUSE frame decode time allowance                   64 bytes
+          4) One maximum-length frame on RX                    1522 bytes
+          5) Round-trip propagation delay of the link (100Mb)    15 bytes
+          ----------       
+          3187 bytes
+
+          I chose to set high-water mark to RX_FIFO_SIZE / 4 (1024 bytes)
+          low-water mark  to RX_FIFO_SIZE / 8 (512 bytes)
+        */
+       r = EMAC_RWMR(EMAC_RX_FIFO_SIZE(gige) / 8 / EMAC_FIFO_ENTRY_SIZE,
+                     EMAC_RX_FIFO_SIZE(gige) / 4 / EMAC_FIFO_ENTRY_SIZE);
+       out_be32(&p->rwmr, r);
+
+       /* Set PAUSE timer to the maximum */
+       out_be32(&p->ptr, 0xffff);
+
+       /* IRQ sources */
+       out_be32(&p->iser, EMAC_ISR_TXPE | EMAC_ISR_RXPE | /* EMAC_ISR_TXUE |
+                EMAC_ISR_RXOE | */ EMAC_ISR_OVR | EMAC_ISR_BP | EMAC_ISR_SE |
+                EMAC_ISR_ALE | EMAC_ISR_BFCS | EMAC_ISR_PTLE | EMAC_ISR_ORE |
+                EMAC_ISR_IRE | EMAC_ISR_TE);
+                
+       /* We need to take GPCS PHY out of isolate mode after EMAC reset */
+       if (emac_phy_gpcs(dev->phy.mode)) 
+               mii_reset_phy(&dev->phy);
+                
+       return 0;
+}
 
-       /* Clear the speed bits and make a read request to the PHY */
-       stacr = ((EMAC_STACR_READ | (reg & 0x1f)) & ~EMAC_STACR_CLK_100MHZ);
-       stacr |= ((mii_id & 0x1F) << 5);
+/* BHs disabled */
+static void emac_reinitialize(struct ocp_enet_private *dev)
+{
+       DBG("%d: reinitialize" NL, dev->def->index);
 
-       out_be32(&emacp->em0stacr, stacr);
+       if (!emac_configure(dev)) {
+               emac_tx_enable(dev);
+               emac_rx_enable(dev);
+       }
+}
 
-       count = 0;
-       while ((((stacr = in_be32(&emacp->em0stacr)) & EMAC_STACR_OC) == 0)
-                                       && (count++ < MDIO_DELAY))
-               udelay(1);
-       MDIO_DEBUG((" (count was %d)\n", count));
+/* BHs disabled */
+static void emac_full_tx_reset(struct net_device *ndev)
+{
+       struct ocp_enet_private *dev = ndev->priv;
+       struct ocp_func_emac_data *emacdata = dev->def->additions;
 
-       if ((stacr & EMAC_STACR_OC) == 0) {
-               printk(KERN_WARNING "%s: PHY read timeout #2!\n", dev->name);
-               return -1;
-       }
+       DBG("%d: full_tx_reset" NL, dev->def->index);
 
-       /* Check for a read error */
-       if (stacr & EMAC_STACR_PHYE) {
-               MDIO_DEBUG(("EMAC MDIO PHY error !\n"));
-               return -1;
-       }
+       emac_tx_disable(dev);
+       mal_disable_tx_channel(dev->mal, emacdata->mal_tx_chan);
+       emac_clean_tx_ring(dev);
+       dev->tx_cnt = dev->tx_slot = dev->ack_slot = 0;
 
-       MDIO_DEBUG((" -> 0x%x\n", stacr >> 16));
+       emac_configure(dev);
 
-       return (stacr >> 16);
+       mal_enable_tx_channel(dev->mal, emacdata->mal_tx_chan);
+       emac_tx_enable(dev);
+       emac_rx_enable(dev);
+
+       netif_wake_queue(ndev);
 }
 
-void emac_phy_write(struct net_device *dev, int mii_id, int reg, int data)
+static int __emac_mdio_read(struct ocp_enet_private *dev, u8 id, u8 reg)
 {
-       int count;
-       uint32_t stacr;
-       struct ocp_enet_private *fep = dev->priv;
-       emac_t *emacp = fep->emacp;
+       struct emac_regs *p = dev->emacp;
+       u32 r;
+       int n;
 
-       MDIO_DEBUG(("%s phy_write, id: 0x%x, reg: 0x%x, data: 0x%x\n",
-                   dev->name, mii_id, reg, data));
+       DBG2("%d: mdio_read(%02x,%02x)" NL, dev->def->index, id, reg);
 
-       /* Enable proper ZMII port */
-       if (fep->zmii_dev)
-               emac_enable_zmii_port(fep->zmii_dev, fep->zmii_input);
+       /* Enable proper MDIO port */
+       zmii_enable_mdio(dev->zmii_dev, dev->zmii_input);
 
-       /* Use the EMAC that has the MDIO port */
-       if (fep->mdio_dev) {
-               dev = fep->mdio_dev;
-               fep = dev->priv;
-               emacp = fep->emacp;
+       /* Wait for management interface to become idle */
+       n = 10;
+       while (!(in_be32(&p->stacr) & EMAC_STACR_OC)) {
+               udelay(1);
+               if (!--n)
+                       goto to;
        }
 
-       count = 0;
-       while ((((stacr = in_be32(&emacp->em0stacr)) & EMAC_STACR_OC) == 0)
-                                       && (count++ < MDIO_DELAY))
+       /* Issue read command */
+       out_be32(&p->stacr,
+                EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_READ |
+                (reg & EMAC_STACR_PRA_MASK)
+                | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT));
+
+       /* Wait for read to complete */
+       n = 100;
+       while (!((r = in_be32(&p->stacr)) & EMAC_STACR_OC)) {
                udelay(1);
-       MDIO_DEBUG((" (count was %d)\n", count));
+               if (!--n)
+                       goto to;
+       }
 
-       if ((stacr & EMAC_STACR_OC) == 0) {
-               printk(KERN_WARNING "%s: PHY write timeout #2!\n", dev->name);
-               return;
+       if (unlikely(r & EMAC_STACR_PHYE)) {
+               DBG("%d: mdio_read(%02x, %02x) failed" NL, dev->def->index,
+                   id, reg);
+               return -EREMOTEIO;
        }
 
-       /* Clear the speed bits and make a read request to the PHY */
+       r = ((r >> EMAC_STACR_PHYD_SHIFT) & EMAC_STACR_PHYD_MASK);
+       DBG2("%d: mdio_read -> %04x" NL, dev->def->index, r);
+       return r;
+      to:
+       DBG("%d: MII management interface timeout (read)" NL, dev->def->index);
+       return -ETIMEDOUT;
+}
 
-       stacr = ((EMAC_STACR_WRITE | (reg & 0x1f)) & ~EMAC_STACR_CLK_100MHZ);
-       stacr |= ((mii_id & 0x1f) << 5) | ((data & 0xffff) << 16);
+static void __emac_mdio_write(struct ocp_enet_private *dev, u8 id, u8 reg,
+                             u16 val)
+{
+       struct emac_regs *p = dev->emacp;
+       int n;
 
-       out_be32(&emacp->em0stacr, stacr);
+       DBG2("%d: mdio_write(%02x,%02x,%04x)" NL, dev->def->index, id, reg,
+            val);
 
-       count = 0;
-       while ((((stacr = in_be32(&emacp->em0stacr)) & EMAC_STACR_OC) == 0)
-                                       && (count++ < MDIO_DELAY))
+       /* Enable proper MDIO port */
+       zmii_enable_mdio(dev->zmii_dev, dev->zmii_input);
+
+       /* Wait for management interface to be idle */
+       n = 10;
+       while (!(in_be32(&p->stacr) & EMAC_STACR_OC)) {
                udelay(1);
-       MDIO_DEBUG((" (count was %d)\n", count));
+               if (!--n)
+                       goto to;
+       }
 
-       if ((stacr & EMAC_STACR_OC) == 0)
-               printk(KERN_WARNING "%s: PHY write timeout #2!\n", dev->name);
+       /* Issue write command */
+       out_be32(&p->stacr,
+                EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_WRITE |
+                (reg & EMAC_STACR_PRA_MASK) |
+                ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |
+                (val << EMAC_STACR_PHYD_SHIFT));
 
-       /* Check for a write error */
-       if ((stacr & EMAC_STACR_PHYE) != 0) {
-               MDIO_DEBUG(("EMAC MDIO PHY error !\n"));
+       /* Wait for write to complete */
+       n = 100;
+       while (!(in_be32(&p->stacr) & EMAC_STACR_OC)) {
+               udelay(1);
+               if (!--n)
+                       goto to;
        }
+       return;
+      to:
+       DBG("%d: MII management interface timeout (write)" NL, dev->def->index);
 }
 
-static void emac_txeob_dev(void *param, u32 chanmask)
+static int emac_mdio_read(struct net_device *ndev, int id, int reg)
 {
-       struct net_device *dev = param;
-       struct ocp_enet_private *fep = dev->priv;
-       unsigned long flags;
-
-       spin_lock_irqsave(&fep->lock, flags);
-
-       PKT_DEBUG(("emac_txeob_dev() entry, tx_cnt: %d\n", fep->tx_cnt));
-
-       while (fep->tx_cnt &&
-              !(fep->tx_desc[fep->ack_slot].ctrl & MAL_TX_CTRL_READY)) {
+       struct ocp_enet_private *dev = ndev->priv;
+       int res;
+
+       local_bh_disable();
+       res = __emac_mdio_read(dev->mdio_dev ? dev->mdio_dev : dev, (u8) id,
+                              (u8) reg);
+       local_bh_enable();
+       return res;
+}
 
-               if (fep->tx_desc[fep->ack_slot].ctrl & MAL_TX_CTRL_LAST) {
-                       /* Tell the system the transmit completed. */
-                       dma_unmap_single(&fep->ocpdev->dev,
-                                        fep->tx_desc[fep->ack_slot].data_ptr,
-                                        fep->tx_desc[fep->ack_slot].data_len,
-                                        DMA_TO_DEVICE);
-                       dev_kfree_skb_irq(fep->tx_skb[fep->ack_slot]);
+static void emac_mdio_write(struct net_device *ndev, int id, int reg, int val)
+{
+       struct ocp_enet_private *dev = ndev->priv;
 
-                       if (fep->tx_desc[fep->ack_slot].ctrl &
-                           (EMAC_TX_ST_EC | EMAC_TX_ST_MC | EMAC_TX_ST_SC))
-                               fep->stats.collisions++;
-               }
+       local_bh_disable();
+       __emac_mdio_write(dev->mdio_dev ? dev->mdio_dev : dev, (u8) id,
+                         (u8) reg, (u16) val);
+       local_bh_enable();
+}
 
-               fep->tx_skb[fep->ack_slot] = (struct sk_buff *)NULL;
-               if (++fep->ack_slot == NUM_TX_BUFF)
-                       fep->ack_slot = 0;
+/* BHs disabled */
+static void emac_set_multicast_list(struct net_device *ndev)
+{
+       struct ocp_enet_private *dev = ndev->priv;
+       struct emac_regs *p = dev->emacp;
+       u32 rmr = emac_iff2rmr(ndev);
+
+       DBG("%d: multicast %08x" NL, dev->def->index, rmr);
+       BUG_ON(!netif_running(dev->ndev));
+
+       /* I decided to relax register access rules here to avoid
+        * full EMAC reset.
+        *
+        * There is a real problem with EMAC4 core if we use MWSW_001 bit 
+        * in MR1 register and do a full EMAC reset.
+        * One TX BD status update is delayed and, after EMAC reset, it 
+        * never happens, resulting in TX hung (it'll be recovered by TX 
+        * timeout handler eventually, but this is just gross).
+        * So we either have to do full TX reset or try to cheat here :)
+        *
+        * The only required change is to RX mode register, so I *think* all
+        * we need is just to stop RX channel. This seems to work on all
+        * tested SoCs.                                                --ebs
+        */
+       emac_rx_disable(dev);
+       if (rmr & EMAC_RMR_MAE)
+               emac_hash_mc(dev);
+       out_be32(&p->rmr, rmr);
+       emac_rx_enable(dev);
+}
 
-               fep->tx_cnt--;
+/* BHs disabled */
+static int emac_resize_rx_ring(struct ocp_enet_private *dev, int new_mtu)
+{
+       struct ocp_func_emac_data *emacdata = dev->def->additions;
+       int rx_sync_size = emac_rx_sync_size(new_mtu);
+       int rx_skb_size = emac_rx_skb_size(new_mtu);
+       int i, ret = 0;
+
+       emac_rx_disable(dev);
+       mal_disable_rx_channel(dev->mal, emacdata->mal_rx_chan);
+
+       if (dev->rx_sg_skb) {
+               ++dev->estats.rx_dropped_resize;
+               dev_kfree_skb(dev->rx_sg_skb);
+               dev->rx_sg_skb = NULL;
        }
-       if (fep->tx_cnt < NUM_TX_BUFF)
-               netif_wake_queue(dev);
 
-       PKT_DEBUG(("emac_txeob_dev() exit, tx_cnt: %d\n", fep->tx_cnt));
+       /* Make a first pass over RX ring and mark BDs ready, dropping 
+        * non-processed packets on the way. We need this as a separate pass
+        * to simplify error recovery in the case of allocation failure later.
+        */
+       for (i = 0; i < NUM_RX_BUFF; ++i) {
+               if (dev->rx_desc[i].ctrl & MAL_RX_CTRL_FIRST)
+                       ++dev->estats.rx_dropped_resize;
 
-       spin_unlock_irqrestore(&fep->lock, flags);
-}
+               dev->rx_desc[i].data_len = 0;
+               dev->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY |
+                   (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
+       }
 
-/*
-  Fill/Re-fill the rx chain with valid ctrl/ptrs.
-  This function will fill from rx_slot up to the parm end.
-  So to completely fill the chain pre-set rx_slot to 0 and
-  pass in an end of 0.
- */
-static void emac_rx_fill(struct net_device *dev, int end)
-{
-       int i;
-       struct ocp_enet_private *fep = dev->priv;
-
-       i = fep->rx_slot;
-       do {
-               /* We don't want the 16 bytes skb_reserve done by dev_alloc_skb,
-                * it breaks our cache line alignement. However, we still allocate
-                * +16 so that we end up allocating the exact same size as
-                * dev_alloc_skb() would do.
-                * Also, because of the skb_res, the max DMA size we give to EMAC
-                * is slighly wrong, causing it to potentially DMA 2 more bytes
-                * from a broken/oversized packet. These 16 bytes will take care
-                * that we don't walk on somebody else toes with that.
-                */
-               fep->rx_skb[i] =
-                   alloc_skb(fep->rx_buffer_size + 16, GFP_ATOMIC);
-
-               if (fep->rx_skb[i] == NULL) {
-                       /* Keep rx_slot here, the next time clean/fill is called
-                        * we will try again before the MAL wraps back here
-                        * If the MAL tries to use this descriptor with
-                        * the EMPTY bit off it will cause the
-                        * rxde interrupt.  That is where we will
-                        * try again to allocate an sk_buff.
-                        */
-                       break;
+       /* Reallocate RX ring only if bigger skb buffers are required */
+       if (rx_skb_size <= dev->rx_skb_size)
+               goto skip;
 
+       /* Second pass, allocate new skbs */
+       for (i = 0; i < NUM_RX_BUFF; ++i) {
+               struct sk_buff *skb = alloc_skb(rx_skb_size, GFP_ATOMIC);
+               if (!skb) {
+                       ret = -ENOMEM;
+                       goto oom;
                }
 
-               if (skb_res)
-                       skb_reserve(fep->rx_skb[i], skb_res);
+               BUG_ON(!dev->rx_skb[i]);
+               dev_kfree_skb(dev->rx_skb[i]);
 
-               /* We must NOT dma_map_single the cache line right after the
-                * buffer, so we must crop our sync size to account for the
-                * reserved space
-                */
-               fep->rx_desc[i].data_ptr =
-                   (unsigned char *)dma_map_single(&fep->ocpdev->dev,
-                                                   (void *)fep->rx_skb[i]->
-                                                   data,
-                                                   fep->rx_buffer_size -
-                                                   skb_res, DMA_FROM_DEVICE);
-
-               /*
-                * Some 4xx implementations use the previously
-                * reserved bits in data_len to encode the MS
-                * 4-bits of a 36-bit physical address (ERPN)
-                * This must be initialized.
-                */
-               fep->rx_desc[i].data_len = 0;
-               fep->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR |
-                   (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
+               skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
+               dev->rx_desc[i].data_ptr =
+                   dma_map_single(dev->ldev, skb->data - 2, rx_sync_size,
+                                  DMA_FROM_DEVICE) + 2;
+               dev->rx_skb[i] = skb;
+       }
+      skip:
+       /* Check if we need to change "Jumbo" bit in MR1 */
+       if ((new_mtu > ETH_DATA_LEN) ^ (dev->ndev->mtu > ETH_DATA_LEN)) {
+               /* This is to prevent starting RX channel in emac_rx_enable() */
+               dev->commac.rx_stopped = 1;
+
+               dev->ndev->mtu = new_mtu;
+               emac_full_tx_reset(dev->ndev);
+       }
 
-       } while ((i = (i + 1) % NUM_RX_BUFF) != end);
+       mal_set_rcbs(dev->mal, emacdata->mal_rx_chan, emac_rx_size(new_mtu));
+      oom:
+       /* Restart RX */
+       dev->commac.rx_stopped = dev->rx_slot = 0;
+       mal_enable_rx_channel(dev->mal, emacdata->mal_rx_chan);
+       emac_rx_enable(dev);
 
-       fep->rx_slot = i;
+       return ret;
 }
 
-static void
-emac_rx_csum(struct net_device *dev, unsigned short ctrl, struct sk_buff *skb)
+/* Process ctx, rtnl_lock semaphore */
+static int emac_change_mtu(struct net_device *ndev, int new_mtu)
 {
-       struct ocp_enet_private *fep = dev->priv;
+       struct ocp_enet_private *dev = ndev->priv;
+       int ret = 0;
 
-       /* Exit if interface has no TAH engine */
-       if (!fep->tah_dev) {
-               skb->ip_summed = CHECKSUM_NONE;
-               return;
-       }
+       if (new_mtu < EMAC_MIN_MTU || new_mtu > EMAC_MAX_MTU)
+               return -EINVAL;
 
-       /* Check for TCP/UDP/IP csum error */
-       if (ctrl & EMAC_CSUM_VER_ERROR) {
-               /* Let the stack verify checksum errors */
-               skb->ip_summed = CHECKSUM_NONE;
-/*             adapter->hw_csum_err++; */
-       } else {
-               /* Csum is good */
-               skb->ip_summed = CHECKSUM_UNNECESSARY;
-/*             adapter->hw_csum_good++; */
-       }
-}
+       DBG("%d: change_mtu(%d)" NL, dev->def->index, new_mtu);
 
-static int emac_rx_clean(struct net_device *dev)
-{
-       int i, b, bnum = 0, buf[6];
-       int error, frame_length;
-       struct ocp_enet_private *fep = dev->priv;
-       unsigned short ctrl;
+       local_bh_disable();
+       if (netif_running(ndev)) {
+               /* Check if we really need to reinitalize RX ring */
+               if (emac_rx_skb_size(ndev->mtu) != emac_rx_skb_size(new_mtu))
+                       ret = emac_resize_rx_ring(dev, new_mtu);
+       }
 
-       i = fep->rx_slot;
+       if (!ret) {
+               ndev->mtu = new_mtu;
+               dev->rx_skb_size = emac_rx_skb_size(new_mtu);
+               dev->rx_sync_size = emac_rx_sync_size(new_mtu);
+       }       
+       local_bh_enable();
 
-       PKT_DEBUG(("emac_rx_clean() entry, rx_slot: %d\n", fep->rx_slot));
+       return ret;
+}
 
-       do {
-               if (fep->rx_skb[i] == NULL)
-                       continue;       /*we have already handled the packet but haved failed to alloc */
-               /* 
-                  since rx_desc is in uncached mem we don't keep reading it directly 
-                  we pull out a local copy of ctrl and do the checks on the copy.
-                */
-               ctrl = fep->rx_desc[i].ctrl;
-               if (ctrl & MAL_RX_CTRL_EMPTY)
-                       break;  /*we don't have any more ready packets */
-
-               if (EMAC_IS_BAD_RX_PACKET(ctrl)) {
-                       fep->stats.rx_errors++;
-                       fep->stats.rx_dropped++;
-
-                       if (ctrl & EMAC_RX_ST_OE)
-                               fep->stats.rx_fifo_errors++;
-                       if (ctrl & EMAC_RX_ST_AE)
-                               fep->stats.rx_frame_errors++;
-                       if (ctrl & EMAC_RX_ST_BFCS)
-                               fep->stats.rx_crc_errors++;
-                       if (ctrl & (EMAC_RX_ST_RP | EMAC_RX_ST_PTL |
-                                   EMAC_RX_ST_ORE | EMAC_RX_ST_IRE))
-                               fep->stats.rx_length_errors++;
-               } else {
-                       if ((ctrl & (MAL_RX_CTRL_FIRST | MAL_RX_CTRL_LAST)) ==
-                           (MAL_RX_CTRL_FIRST | MAL_RX_CTRL_LAST)) {
-                               /* Single descriptor packet */
-                               emac_rx_csum(dev, ctrl, fep->rx_skb[i]);
-                               /* Send the skb up the chain. */
-                               frame_length = fep->rx_desc[i].data_len - 4;
-                               skb_put(fep->rx_skb[i], frame_length);
-                               fep->rx_skb[i]->dev = dev;
-                               fep->rx_skb[i]->protocol =
-                                   eth_type_trans(fep->rx_skb[i], dev);
-                               error = netif_rx(fep->rx_skb[i]);
-
-                               if ((error == NET_RX_DROP) ||
-                                   (error == NET_RX_BAD)) {
-                                       fep->stats.rx_dropped++;
-                               } else {
-                                       fep->stats.rx_packets++;
-                                       fep->stats.rx_bytes += frame_length;
-                               }
-                               fep->rx_skb[i] = NULL;
-                       } else {
-                               /* Multiple descriptor packet */
-                               if (ctrl & MAL_RX_CTRL_FIRST) {
-                                       if (fep->rx_desc[(i + 1) % NUM_RX_BUFF].
-                                           ctrl & MAL_RX_CTRL_EMPTY)
-                                               break;
-                                       bnum = 0;
-                                       buf[bnum] = i;
-                                       ++bnum;
-                                       continue;
-                               }
-                               if (((ctrl & MAL_RX_CTRL_FIRST) !=
-                                    MAL_RX_CTRL_FIRST) &&
-                                   ((ctrl & MAL_RX_CTRL_LAST) !=
-                                    MAL_RX_CTRL_LAST)) {
-                                       if (fep->rx_desc[(i + 1) %
-                                                        NUM_RX_BUFF].ctrl &
-                                           MAL_RX_CTRL_EMPTY) {
-                                               i = buf[0];
-                                               break;
-                                       }
-                                       buf[bnum] = i;
-                                       ++bnum;
-                                       continue;
-                               }
-                               if (ctrl & MAL_RX_CTRL_LAST) {
-                                       buf[bnum] = i;
-                                       ++bnum;
-                                       skb_put(fep->rx_skb[buf[0]],
-                                               fep->rx_desc[buf[0]].data_len);
-                                       for (b = 1; b < bnum; b++) {
-                                               /*
-                                                * MAL is braindead, we need
-                                                * to copy the remainder
-                                                * of the packet from the
-                                                * latter descriptor buffers
-                                                * to the first skb. Then
-                                                * dispose of the source
-                                                * skbs.
-                                                *
-                                                * Once the stack is fixed
-                                                * to handle frags on most
-                                                * protocols we can generate
-                                                * a fragmented skb with
-                                                * no copies.
-                                                */
-                                               memcpy(fep->rx_skb[buf[0]]->
-                                                      data +
-                                                      fep->rx_skb[buf[0]]->len,
-                                                      fep->rx_skb[buf[b]]->
-                                                      data,
-                                                      fep->rx_desc[buf[b]].
-                                                      data_len);
-                                               skb_put(fep->rx_skb[buf[0]],
-                                                       fep->rx_desc[buf[b]].
-                                                       data_len);
-                                               dma_unmap_single(&fep->ocpdev->
-                                                                dev,
-                                                                fep->
-                                                                rx_desc[buf
-                                                                        [b]].
-                                                                data_ptr,
-                                                                fep->
-                                                                rx_desc[buf
-                                                                        [b]].
-                                                                data_len,
-                                                                DMA_FROM_DEVICE);
-                                               dev_kfree_skb(fep->
-                                                             rx_skb[buf[b]]);
-                                       }
-                                       emac_rx_csum(dev, ctrl,
-                                                    fep->rx_skb[buf[0]]);
-
-                                       fep->rx_skb[buf[0]]->dev = dev;
-                                       fep->rx_skb[buf[0]]->protocol =
-                                           eth_type_trans(fep->rx_skb[buf[0]],
-                                                          dev);
-                                       error = netif_rx(fep->rx_skb[buf[0]]);
-
-                                       if ((error == NET_RX_DROP)
-                                           || (error == NET_RX_BAD)) {
-                                               fep->stats.rx_dropped++;
-                                       } else {
-                                               fep->stats.rx_packets++;
-                                               fep->stats.rx_bytes +=
-                                                   fep->rx_skb[buf[0]]->len;
-                                       }
-                                       for (b = 0; b < bnum; b++)
-                                               fep->rx_skb[buf[b]] = NULL;
-                               }
-                       }
+static void emac_clean_tx_ring(struct ocp_enet_private *dev)
+{
+       int i;
+       for (i = 0; i < NUM_TX_BUFF; ++i) {
+               if (dev->tx_skb[i]) {
+                       dev_kfree_skb(dev->tx_skb[i]);
+                       dev->tx_skb[i] = NULL;
+                       if (dev->tx_desc[i].ctrl & MAL_TX_CTRL_READY)
+                               ++dev->estats.tx_dropped;
                }
-       } while ((i = (i + 1) % NUM_RX_BUFF) != fep->rx_slot);
-
-       PKT_DEBUG(("emac_rx_clean() exit, rx_slot: %d\n", fep->rx_slot));
-
-       return i;
+               dev->tx_desc[i].ctrl = 0;
+               dev->tx_desc[i].data_ptr = 0;
+       }
 }
 
-static void emac_rxeob_dev(void *param, u32 chanmask)
+static void emac_clean_rx_ring(struct ocp_enet_private *dev)
 {
-       struct net_device *dev = param;
-       struct ocp_enet_private *fep = dev->priv;
-       unsigned long flags;
-       int n;
+       int i;
+       for (i = 0; i < NUM_RX_BUFF; ++i)
+               if (dev->rx_skb[i]) {
+                       dev->rx_desc[i].ctrl = 0;
+                       dev_kfree_skb(dev->rx_skb[i]);
+                       dev->rx_skb[i] = NULL;
+                       dev->rx_desc[i].data_ptr = 0;
+               }
 
-       spin_lock_irqsave(&fep->lock, flags);
-       if ((n = emac_rx_clean(dev)) != fep->rx_slot)
-               emac_rx_fill(dev, n);
-       spin_unlock_irqrestore(&fep->lock, flags);
+       if (dev->rx_sg_skb) {
+               dev_kfree_skb(dev->rx_sg_skb);
+               dev->rx_sg_skb = NULL;
+       }
 }
 
-/*
- * This interrupt should never occurr, we don't program
- * the MAL for contiunous mode.
- */
-static void emac_txde_dev(void *param, u32 chanmask)
+static inline int emac_alloc_rx_skb(struct ocp_enet_private *dev, int slot,
+                                   int flags)
 {
-       struct net_device *dev = param;
-       struct ocp_enet_private *fep = dev->priv;
+       struct sk_buff *skb = alloc_skb(dev->rx_skb_size, flags);
+       if (unlikely(!skb))
+               return -ENOMEM;
 
-       printk(KERN_WARNING "%s: transmit descriptor error\n", dev->name);
+       dev->rx_skb[slot] = skb;
+       dev->rx_desc[slot].data_len = 0;
 
-       emac_mac_dump(dev);
-       emac_mal_dump(dev);
+       skb_reserve(skb, EMAC_RX_SKB_HEADROOM + 2);
+       dev->rx_desc[slot].data_ptr = 
+           dma_map_single(dev->ldev, skb->data - 2, dev->rx_sync_size, 
+                          DMA_FROM_DEVICE) + 2;
+       barrier();
+       dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
+           (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
 
-       /* Reenable the transmit channel */
-       mal_enable_tx_channels(fep->mal, fep->commac.tx_chan_mask);
+       return 0;
 }
 
-/*
- * This interrupt should be very rare at best.  This occurs when
- * the hardware has a problem with the receive descriptors.  The manual
- * states that it occurs when the hardware cannot the receive descriptor
- * empty bit is not set.  The recovery mechanism will be to
- * traverse through the descriptors, handle any that are marked to be
- * handled and reinitialize each along the way.  At that point the driver
- * will be restarted.
- */
-static void emac_rxde_dev(void *param, u32 chanmask)
+static void emac_print_link_status(struct ocp_enet_private *dev)
 {
-       struct net_device *dev = param;
-       struct ocp_enet_private *fep = dev->priv;
-       unsigned long flags;
-
-       if (net_ratelimit()) {
-               printk(KERN_WARNING "%s: receive descriptor error\n",
-                      fep->ndev->name);
+       if (netif_carrier_ok(dev->ndev))
+               printk(KERN_INFO "%s: link is up, %d %s%s\n",
+                      dev->ndev->name, dev->phy.speed,
+                      dev->phy.duplex == DUPLEX_FULL ? "FDX" : "HDX",
+                      dev->phy.pause ? ", pause enabled" :
+                      dev->phy.asym_pause ? ", assymetric pause enabled" : "");
+       else
+               printk(KERN_INFO "%s: link is down\n", dev->ndev->name);
+}
 
-               emac_mac_dump(dev);
-               emac_mal_dump(dev);
-               emac_desc_dump(dev);
+/* Process ctx, rtnl_lock semaphore */
+static int emac_open(struct net_device *ndev)
+{
+       struct ocp_enet_private *dev = ndev->priv;
+       struct ocp_func_emac_data *emacdata = dev->def->additions;
+       int err, i;
+
+       DBG("%d: open" NL, dev->def->index);
+
+       /* Setup error IRQ handler */
+       err = request_irq(dev->def->irq, emac_irq, 0, "EMAC", dev);
+       if (err) {
+               printk(KERN_ERR "%s: failed to request IRQ %d\n",
+                      ndev->name, dev->def->irq);
+               return err;
        }
 
-       /* Disable RX channel */
-       spin_lock_irqsave(&fep->lock, flags);
-       mal_disable_rx_channels(fep->mal, fep->commac.rx_chan_mask);
-
-       /* For now, charge the error against all emacs */
-       fep->stats.rx_errors++;
-
-       /* so do we have any good packets still? */
-       emac_rx_clean(dev);
-
-       /* When the interface is restarted it resets processing to the
-        *  first descriptor in the table.
-        */
-
-       fep->rx_slot = 0;
-       emac_rx_fill(dev, 0);
+       /* Allocate RX ring */
+       for (i = 0; i < NUM_RX_BUFF; ++i)
+               if (emac_alloc_rx_skb(dev, i, GFP_KERNEL)) {
+                       printk(KERN_ERR "%s: failed to allocate RX ring\n",
+                              ndev->name);
+                       goto oom;
+               }
 
-       set_mal_dcrn(fep->mal, DCRN_MALRXEOBISR, fep->commac.rx_chan_mask);
-       set_mal_dcrn(fep->mal, DCRN_MALRXDEIR, fep->commac.rx_chan_mask);
+       local_bh_disable();
+       dev->tx_cnt = dev->tx_slot = dev->ack_slot = dev->rx_slot =
+           dev->commac.rx_stopped = 0;
+       dev->rx_sg_skb = NULL;
+
+       if (dev->phy.address >= 0) {
+               int link_poll_interval;
+               if (dev->phy.def->ops->poll_link(&dev->phy)) {
+                       dev->phy.def->ops->read_link(&dev->phy);
+                       EMAC_RX_CLK_DEFAULT(dev->def->index);
+                       netif_carrier_on(dev->ndev);
+                       link_poll_interval = PHY_POLL_LINK_ON;
+               } else {
+                       EMAC_RX_CLK_TX(dev->def->index);
+                       netif_carrier_off(dev->ndev);
+                       link_poll_interval = PHY_POLL_LINK_OFF;
+               }
+               mod_timer(&dev->link_timer, jiffies + link_poll_interval);
+               emac_print_link_status(dev);
+       } else
+               netif_carrier_on(dev->ndev);
+
+       emac_configure(dev);
+       mal_poll_add(dev->mal, &dev->commac);
+       mal_enable_tx_channel(dev->mal, emacdata->mal_tx_chan);
+       mal_set_rcbs(dev->mal, emacdata->mal_rx_chan, emac_rx_size(ndev->mtu));
+       mal_enable_rx_channel(dev->mal, emacdata->mal_rx_chan);
+       emac_tx_enable(dev);
+       emac_rx_enable(dev);
+       netif_start_queue(ndev);
+       local_bh_enable();
 
-       /* Reenable the receive channels */
-       mal_enable_rx_channels(fep->mal, fep->commac.rx_chan_mask);
-       spin_unlock_irqrestore(&fep->lock, flags);
+       return 0;
+      oom:
+       emac_clean_rx_ring(dev);
+       free_irq(dev->def->irq, dev);
+       return -ENOMEM;
 }
 
-static irqreturn_t
-emac_mac_irq(int irq, void *dev_instance, struct pt_regs *regs)
+/* BHs disabled */
+static int emac_link_differs(struct ocp_enet_private *dev)
 {
-       struct net_device *dev = dev_instance;
-       struct ocp_enet_private *fep = dev->priv;
-       emac_t *emacp = fep->emacp;
-       unsigned long tmp_em0isr;
+       u32 r = in_be32(&dev->emacp->mr1);
 
-       /* EMAC interrupt */
-       tmp_em0isr = in_be32(&emacp->em0isr);
-       if (tmp_em0isr & (EMAC_ISR_TE0 | EMAC_ISR_TE1)) {
-               /* This error is a hard transmit error - could retransmit */
-               fep->stats.tx_errors++;
+       int duplex = r & EMAC_MR1_FDE ? DUPLEX_FULL : DUPLEX_HALF;
+       int speed, pause, asym_pause;
 
-               /* Reenable the transmit channel */
-               mal_enable_tx_channels(fep->mal, fep->commac.tx_chan_mask);
+       if (r & (EMAC_MR1_MF_1000 | EMAC_MR1_MF_1000GPCS))
+               speed = SPEED_1000;
+       else if (r & EMAC_MR1_MF_100)
+               speed = SPEED_100;
+       else
+               speed = SPEED_10;
 
-       } else {
-               fep->stats.rx_errors++;
+       switch (r & (EMAC_MR1_EIFC | EMAC_MR1_APP)) {
+       case (EMAC_MR1_EIFC | EMAC_MR1_APP):
+               pause = 1;
+               asym_pause = 0;
+               break;
+       case EMAC_MR1_APP:
+               pause = 0;
+               asym_pause = 1;
+               break;
+       default:
+               pause = asym_pause = 0;
        }
-
-       if (tmp_em0isr & EMAC_ISR_RP)
-               fep->stats.rx_length_errors++;
-       if (tmp_em0isr & EMAC_ISR_ALE)
-               fep->stats.rx_frame_errors++;
-       if (tmp_em0isr & EMAC_ISR_BFCS)
-               fep->stats.rx_crc_errors++;
-       if (tmp_em0isr & EMAC_ISR_PTLE)
-               fep->stats.rx_length_errors++;
-       if (tmp_em0isr & EMAC_ISR_ORE)
-               fep->stats.rx_length_errors++;
-       if (tmp_em0isr & EMAC_ISR_TE0)
-               fep->stats.tx_aborted_errors++;
-
-       emac_err_dump(dev, tmp_em0isr);
-
-       out_be32(&emacp->em0isr, tmp_em0isr);
-
-       return IRQ_HANDLED;
+       return speed != dev->phy.speed || duplex != dev->phy.duplex ||
+           pause != dev->phy.pause || asym_pause != dev->phy.asym_pause;
 }
 
-static int emac_start_xmit(struct sk_buff *skb, struct net_device *dev)
+/* BHs disabled */
+static void emac_link_timer(unsigned long data)
 {
-       unsigned short ctrl;
-       unsigned long flags;
-       struct ocp_enet_private *fep = dev->priv;
-       emac_t *emacp = fep->emacp;
-       int len = skb->len;
-       unsigned int offset = 0, size, f, tx_slot_first;
-       unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
+       struct ocp_enet_private *dev = (struct ocp_enet_private *)data;
+       int link_poll_interval;
 
-       spin_lock_irqsave(&fep->lock, flags);
+       DBG2("%d: link timer" NL, dev->def->index);
 
-       len -= skb->data_len;
+       if (dev->phy.def->ops->poll_link(&dev->phy)) {
+               if (!netif_carrier_ok(dev->ndev)) {
+                       EMAC_RX_CLK_DEFAULT(dev->def->index);
 
-       if ((fep->tx_cnt + nr_frags + len / DESC_BUF_SIZE + 1) > NUM_TX_BUFF) {
-               PKT_DEBUG(("emac_start_xmit() stopping queue\n"));
-               netif_stop_queue(dev);
-               spin_unlock_irqrestore(&fep->lock, flags);
-               return -EBUSY;
-       }
+                       /* Get new link parameters */
+                       dev->phy.def->ops->read_link(&dev->phy);
 
-       tx_slot_first = fep->tx_slot;
+                       if (dev->tah_dev || emac_link_differs(dev))
+                               emac_full_tx_reset(dev->ndev);
 
-       while (len) {
-               size = min(len, DESC_BUF_SIZE);
-
-               fep->tx_desc[fep->tx_slot].data_len = (short)size;
-               fep->tx_desc[fep->tx_slot].data_ptr =
-                   (unsigned char *)dma_map_single(&fep->ocpdev->dev,
-                                                   (void *)((unsigned int)skb->
-                                                            data + offset),
-                                                   size, DMA_TO_DEVICE);
-
-               ctrl = EMAC_TX_CTRL_DFLT;
-               if (fep->tx_slot != tx_slot_first)
-                       ctrl |= MAL_TX_CTRL_READY;
-               if ((NUM_TX_BUFF - 1) == fep->tx_slot)
-                       ctrl |= MAL_TX_CTRL_WRAP;
-               if (!nr_frags && (len == size)) {
-                       ctrl |= MAL_TX_CTRL_LAST;
-                       fep->tx_skb[fep->tx_slot] = skb;
+                       netif_carrier_on(dev->ndev);
+                       emac_print_link_status(dev);
+               }
+               link_poll_interval = PHY_POLL_LINK_ON;
+       } else {
+               if (netif_carrier_ok(dev->ndev)) {
+                       EMAC_RX_CLK_TX(dev->def->index);
+#if defined(CONFIG_IBM_EMAC_PHY_RX_CLK_FIX)
+                       emac_reinitialize(dev);
+#endif
+                       netif_carrier_off(dev->ndev);
+                       emac_print_link_status(dev);
                }
-               if (skb->ip_summed == CHECKSUM_HW)
-                       ctrl |= EMAC_TX_CTRL_TAH_CSUM;
 
-               fep->tx_desc[fep->tx_slot].ctrl = ctrl;
+               /* Retry reset if the previous attempt failed.
+                * This is needed mostly for CONFIG_IBM_EMAC_PHY_RX_CLK_FIX
+                * case, but I left it here because it shouldn't trigger for
+                * sane PHYs anyway.
+                */
+               if (unlikely(dev->reset_failed))
+                       emac_reinitialize(dev);
 
-               len -= size;
-               offset += size;
+               link_poll_interval = PHY_POLL_LINK_OFF;
+       }
+       mod_timer(&dev->link_timer, jiffies + link_poll_interval);
+}
 
-               /* Bump tx count */
-               if (++fep->tx_cnt == NUM_TX_BUFF)
-                       netif_stop_queue(dev);
+/* BHs disabled */
+static void emac_force_link_update(struct ocp_enet_private *dev)
+{
+       netif_carrier_off(dev->ndev);
+       if (timer_pending(&dev->link_timer))
+               mod_timer(&dev->link_timer, jiffies + PHY_POLL_LINK_OFF);
+}
 
-               /* Next descriptor */
-               if (++fep->tx_slot == NUM_TX_BUFF)
-                       fep->tx_slot = 0;
-       }
+/* Process ctx, rtnl_lock semaphore */
+static int emac_close(struct net_device *ndev)
+{
+       struct ocp_enet_private *dev = ndev->priv;
+       struct ocp_func_emac_data *emacdata = dev->def->additions;
 
-       for (f = 0; f < nr_frags; f++) {
-               struct skb_frag_struct *frag;
+       DBG("%d: close" NL, dev->def->index);
 
-               frag = &skb_shinfo(skb)->frags[f];
-               len = frag->size;
-               offset = 0;
-
-               while (len) {
-                       size = min(len, DESC_BUF_SIZE);
-
-                       dma_map_page(&fep->ocpdev->dev,
-                                    frag->page,
-                                    frag->page_offset + offset,
-                                    size, DMA_TO_DEVICE);
-
-                       ctrl = EMAC_TX_CTRL_DFLT | MAL_TX_CTRL_READY;
-                       if ((NUM_TX_BUFF - 1) == fep->tx_slot)
-                               ctrl |= MAL_TX_CTRL_WRAP;
-                       if ((f == (nr_frags - 1)) && (len == size)) {
-                               ctrl |= MAL_TX_CTRL_LAST;
-                               fep->tx_skb[fep->tx_slot] = skb;
-                       }
+       local_bh_disable();
 
-                       if (skb->ip_summed == CHECKSUM_HW)
-                               ctrl |= EMAC_TX_CTRL_TAH_CSUM;
+       if (dev->phy.address >= 0)
+               del_timer_sync(&dev->link_timer);
 
-                       fep->tx_desc[fep->tx_slot].data_len = (short)size;
-                       fep->tx_desc[fep->tx_slot].data_ptr =
-                           (char *)((page_to_pfn(frag->page) << PAGE_SHIFT) +
-                                    frag->page_offset + offset);
-                       fep->tx_desc[fep->tx_slot].ctrl = ctrl;
+       netif_stop_queue(ndev);
+       emac_rx_disable(dev);
+       emac_tx_disable(dev);
+       mal_disable_rx_channel(dev->mal, emacdata->mal_rx_chan);
+       mal_disable_tx_channel(dev->mal, emacdata->mal_tx_chan);
+       mal_poll_del(dev->mal, &dev->commac);
+       local_bh_enable();
 
-                       len -= size;
-                       offset += size;
+       emac_clean_tx_ring(dev);
+       emac_clean_rx_ring(dev);
+       free_irq(dev->def->irq, dev);
 
-                       /* Bump tx count */
-                       if (++fep->tx_cnt == NUM_TX_BUFF)
-                               netif_stop_queue(dev);
+       return 0;
+}
 
-                       /* Next descriptor */
-                       if (++fep->tx_slot == NUM_TX_BUFF)
-                               fep->tx_slot = 0;
-               }
+static inline u16 emac_tx_csum(struct ocp_enet_private *dev,
+                              struct sk_buff *skb)
+{
+#if defined(CONFIG_IBM_EMAC_TAH)
+       if (skb->ip_summed == CHECKSUM_HW) {
+               ++dev->stats.tx_packets_csum;
+               return EMAC_TX_CTRL_TAH_CSUM;
        }
+#endif
+       return 0;
+}
 
-       /*
-        * Deferred set READY on first descriptor of packet to
-        * avoid TX MAL race.
-        */
-       fep->tx_desc[tx_slot_first].ctrl |= MAL_TX_CTRL_READY;
-
-       /* Send the packet out. */
-       out_be32(&emacp->em0tmr0, EMAC_TMR0_XMIT);
+static inline int emac_xmit_finish(struct ocp_enet_private *dev, int len)
+{
+       struct emac_regs *p = dev->emacp;
+       struct net_device *ndev = dev->ndev;
 
-       fep->stats.tx_packets++;
-       fep->stats.tx_bytes += skb->len;
+       /* Send the packet out */
+       out_be32(&p->tmr0, EMAC_TMR0_XMIT);
 
-       PKT_DEBUG(("emac_start_xmit() exitn"));
+       if (unlikely(++dev->tx_cnt == NUM_TX_BUFF)) {
+               netif_stop_queue(ndev);
+               DBG2("%d: stopped TX queue" NL, dev->def->index);
+       }
 
-       spin_unlock_irqrestore(&fep->lock, flags);
+       ndev->trans_start = jiffies;
+       ++dev->stats.tx_packets;
+       dev->stats.tx_bytes += len;
 
        return 0;
 }
 
-static int emac_adjust_to_link(struct ocp_enet_private *fep)
+/* BHs disabled */
+static int emac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 {
-       emac_t *emacp = fep->emacp;
-       unsigned long mode_reg;
-       int full_duplex, speed;
+       struct ocp_enet_private *dev = ndev->priv;
+       unsigned int len = skb->len;
+       int slot;
 
-       full_duplex = 0;
-       speed = SPEED_10;
+       u16 ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
+           MAL_TX_CTRL_LAST | emac_tx_csum(dev, skb);
 
-       /* set mode register 1 defaults */
-       mode_reg = EMAC_M1_DEFAULT;
-
-       /* Read link mode on PHY */
-       if (fep->phy_mii.def->ops->read_link(&fep->phy_mii) == 0) {
-               /* If an error occurred, we don't deal with it yet */
-               full_duplex = (fep->phy_mii.duplex == DUPLEX_FULL);
-               speed = fep->phy_mii.speed;
+       slot = dev->tx_slot++;
+       if (dev->tx_slot == NUM_TX_BUFF) {
+               dev->tx_slot = 0;
+               ctrl |= MAL_TX_CTRL_WRAP;
        }
 
+       DBG2("%d: xmit(%u) %d" NL, dev->def->index, len, slot);
 
-       /* set speed (default is 10Mb) */
-       switch (speed) {
-       case SPEED_1000:
-               mode_reg |= EMAC_M1_RFS_16K;
-               if (fep->rgmii_dev) {
-                       struct ibm_ocp_rgmii *rgmii = RGMII_PRIV(fep->rgmii_dev);
-
-                       if ((rgmii->mode[fep->rgmii_input] == RTBI)
-                           || (rgmii->mode[fep->rgmii_input] == TBI))
-                               mode_reg |= EMAC_M1_MF_1000GPCS;
-                       else
-                               mode_reg |= EMAC_M1_MF_1000MBPS;
-
-                       emac_rgmii_port_speed(fep->rgmii_dev, fep->rgmii_input,
-                                             1000);
-               }
-               break;
-       case SPEED_100:
-               mode_reg |= EMAC_M1_MF_100MBPS | EMAC_M1_RFS_4K;
-               if (fep->rgmii_dev)
-                       emac_rgmii_port_speed(fep->rgmii_dev, fep->rgmii_input,
-                                             100);
-               if (fep->zmii_dev)
-                       emac_zmii_port_speed(fep->zmii_dev, fep->zmii_input,
-                                            100);
-               break;
-       case SPEED_10:
-       default:
-               mode_reg = (mode_reg & ~EMAC_M1_MF_100MBPS) | EMAC_M1_RFS_4K;
-               if (fep->rgmii_dev)
-                       emac_rgmii_port_speed(fep->rgmii_dev, fep->rgmii_input,
-                                             10);
-               if (fep->zmii_dev)
-                       emac_zmii_port_speed(fep->zmii_dev, fep->zmii_input,
-                                            10);
-       }
-
-       if (full_duplex)
-               mode_reg |= EMAC_M1_FDE | EMAC_M1_EIFC | EMAC_M1_IST;
-       else
-               mode_reg &= ~(EMAC_M1_FDE | EMAC_M1_EIFC | EMAC_M1_ILE);
+       dev->tx_skb[slot] = skb;
+       dev->tx_desc[slot].data_ptr = dma_map_single(dev->ldev, skb->data, len,
+                                                    DMA_TO_DEVICE);
+       dev->tx_desc[slot].data_len = (u16) len;
+       barrier();
+       dev->tx_desc[slot].ctrl = ctrl;
 
-       LINK_DEBUG(("%s: adjust to link, speed: %d, duplex: %d, opened: %d\n",
-                   fep->ndev->name, speed, full_duplex, fep->opened));
-
-       printk(KERN_INFO "%s: Speed: %d, %s duplex.\n",
-              fep->ndev->name, speed, full_duplex ? "Full" : "Half");
-       if (fep->opened)
-               out_be32(&emacp->em0mr1, mode_reg);
-
-       return 0;
+       return emac_xmit_finish(dev, len);
 }
 
-static int emac_set_mac_address(struct net_device *ndev, void *p)
+#if defined(CONFIG_IBM_EMAC_TAH)
+static inline int emac_xmit_split(struct ocp_enet_private *dev, int slot,
+                                 u32 pd, int len, int last, u16 base_ctrl)
 {
-       struct ocp_enet_private *fep = ndev->priv;
-       emac_t *emacp = fep->emacp;
-       struct sockaddr *addr = p;
+       while (1) {
+               u16 ctrl = base_ctrl;
+               int chunk = min(len, MAL_MAX_TX_SIZE);
+               len -= chunk;
 
-       if (!is_valid_ether_addr(addr->sa_data))
-               return -EADDRNOTAVAIL;
+               slot = (slot + 1) % NUM_TX_BUFF;
 
-       memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
+               if (last && !len)
+                       ctrl |= MAL_TX_CTRL_LAST;
+               if (slot == NUM_TX_BUFF - 1)
+                       ctrl |= MAL_TX_CTRL_WRAP;
 
-       /* set the high address */
-       out_be32(&emacp->em0iahr,
-                (fep->ndev->dev_addr[0] << 8) | fep->ndev->dev_addr[1]);
+               dev->tx_skb[slot] = NULL;
+               dev->tx_desc[slot].data_ptr = pd;
+               dev->tx_desc[slot].data_len = (u16) chunk;
+               dev->tx_desc[slot].ctrl = ctrl;
+               ++dev->tx_cnt;
 
-       /* set the low address */
-       out_be32(&emacp->em0ialr,
-                (fep->ndev->dev_addr[2] << 24) | (fep->ndev->dev_addr[3] << 16)
-                | (fep->ndev->dev_addr[4] << 8) | fep->ndev->dev_addr[5]);
+               if (!len)
+                       break;
 
-       return 0;
+               pd += chunk;
+       }
+       return slot;
 }
 
-static int emac_change_mtu(struct net_device *dev, int new_mtu)
+/* BHs disabled (SG version for TAH equipped EMACs) */
+static int emac_start_xmit_sg(struct sk_buff *skb, struct net_device *ndev)
 {
-       struct ocp_enet_private *fep = dev->priv;
-       int old_mtu = dev->mtu;
-       unsigned long mode_reg;
-       emac_t *emacp = fep->emacp;
-       u32 em0mr0;
-       int i, full;
-       unsigned long flags;
+       struct ocp_enet_private *dev = ndev->priv;
+       int nr_frags = skb_shinfo(skb)->nr_frags;
+       int len = skb->len, chunk;
+       int slot, i;
+       u16 ctrl;
+       u32 pd;
 
-       if ((new_mtu < EMAC_MIN_MTU) || (new_mtu > EMAC_MAX_MTU)) {
-               printk(KERN_ERR
-                      "emac: Invalid MTU setting, MTU must be between %d and %d\n",
-                      EMAC_MIN_MTU, EMAC_MAX_MTU);
-               return -EINVAL;
-       }
+       /* This is common "fast" path */
+       if (likely(!nr_frags && len <= MAL_MAX_TX_SIZE))
+               return emac_start_xmit(skb, ndev);
 
-       if (old_mtu != new_mtu && netif_running(dev)) {
-               /* Stop rx engine */
-               em0mr0 = in_be32(&emacp->em0mr0);
-               out_be32(&emacp->em0mr0, em0mr0 & ~EMAC_M0_RXE);
-
-               /* Wait for descriptors to be empty */
-               do {
-                       full = 0;
-                       for (i = 0; i < NUM_RX_BUFF; i++)
-                               if (!(fep->rx_desc[i].ctrl & MAL_RX_CTRL_EMPTY)) {
-                                       printk(KERN_NOTICE
-                                              "emac: RX ring is still full\n");
-                                       full = 1;
-                               }
-               } while (full);
-
-               spin_lock_irqsave(&fep->lock, flags);
-
-               mal_disable_rx_channels(fep->mal, fep->commac.rx_chan_mask);
-
-               /* Destroy all old rx skbs */
-               for (i = 0; i < NUM_RX_BUFF; i++) {
-                       dma_unmap_single(&fep->ocpdev->dev,
-                                        fep->rx_desc[i].data_ptr,
-                                        fep->rx_desc[i].data_len,
-                                        DMA_FROM_DEVICE);
-                       dev_kfree_skb(fep->rx_skb[i]);
-                       fep->rx_skb[i] = NULL;
-               }
+       len -= skb->data_len;
 
-               /* Set new rx_buffer_size, jumbo cap, and advertise new mtu */
-               mode_reg = in_be32(&emacp->em0mr1);
-               if (new_mtu > ENET_DEF_MTU_SIZE) {
-                       mode_reg |= EMAC_M1_JUMBO_ENABLE;
-                       fep->rx_buffer_size = EMAC_MAX_FRAME;
-               } else {
-                       mode_reg &= ~EMAC_M1_JUMBO_ENABLE;
-                       fep->rx_buffer_size = ENET_DEF_BUF_SIZE;
-               }
-               dev->mtu = new_mtu;
-               out_be32(&emacp->em0mr1, mode_reg);
+       /* Note, this is only an *estimation*, we can still run out of empty
+        * slots because of the additional fragmentation into
+        * MAL_MAX_TX_SIZE-sized chunks
+        */
+       if (unlikely(dev->tx_cnt + nr_frags + mal_tx_chunks(len) > NUM_TX_BUFF))
+               goto stop_queue;
+
+       ctrl = EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP | MAL_TX_CTRL_READY |
+           emac_tx_csum(dev, skb);
+       slot = dev->tx_slot;
+
+       /* skb data */
+       dev->tx_skb[slot] = NULL;
+       chunk = min(len, MAL_MAX_TX_SIZE);
+       dev->tx_desc[slot].data_ptr = pd =
+           dma_map_single(dev->ldev, skb->data, len, DMA_TO_DEVICE);
+       dev->tx_desc[slot].data_len = (u16) chunk;
+       len -= chunk;
+       if (unlikely(len))
+               slot = emac_xmit_split(dev, slot, pd + chunk, len, !nr_frags,
+                                      ctrl);
+       /* skb fragments */
+       for (i = 0; i < nr_frags; ++i) {
+               struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
+               len = frag->size;
 
-               /* Re-init rx skbs */
-               fep->rx_slot = 0;
-               emac_rx_fill(dev, 0);
+               if (unlikely(dev->tx_cnt + mal_tx_chunks(len) >= NUM_TX_BUFF))
+                       goto undo_frame;
 
-               /* Restart the rx engine */
-               mal_enable_rx_channels(fep->mal, fep->commac.rx_chan_mask);
-               out_be32(&emacp->em0mr0, em0mr0 | EMAC_M0_RXE);
+               pd = dma_map_page(dev->ldev, frag->page, frag->page_offset, len,
+                                 DMA_TO_DEVICE);
 
-               spin_unlock_irqrestore(&fep->lock, flags);
+               slot = emac_xmit_split(dev, slot, pd, len, i == nr_frags - 1,
+                                      ctrl);
        }
 
-       return 0;
-}
+       DBG2("%d: xmit_sg(%u) %d - %d" NL, dev->def->index, skb->len,
+            dev->tx_slot, slot);
 
-static void __emac_set_multicast_list(struct net_device *dev)
-{
-       struct ocp_enet_private *fep = dev->priv;
-       emac_t *emacp = fep->emacp;
-       u32 rmr = in_be32(&emacp->em0rmr);
+       /* Attach skb to the last slot so we don't release it too early */
+       dev->tx_skb[slot] = skb;
 
-       /* First clear all special bits, they can be set later */
-       rmr &= ~(EMAC_RMR_PME | EMAC_RMR_PMME | EMAC_RMR_MAE);
+       /* Send the packet out */
+       if (dev->tx_slot == NUM_TX_BUFF - 1)
+               ctrl |= MAL_TX_CTRL_WRAP;
+       barrier();
+       dev->tx_desc[dev->tx_slot].ctrl = ctrl;
+       dev->tx_slot = (slot + 1) % NUM_TX_BUFF;
 
-       if (dev->flags & IFF_PROMISC) {
-               rmr |= EMAC_RMR_PME;
-       } else if (dev->flags & IFF_ALLMULTI || 32 < dev->mc_count) {
-               /*
-                * Must be setting up to use multicast
-                * Now check for promiscuous multicast
-                */
-               rmr |= EMAC_RMR_PMME;
-       } else if (dev->flags & IFF_MULTICAST && 0 < dev->mc_count) {
-               unsigned short em0gaht[4] = { 0, 0, 0, 0 };
-               struct dev_mc_list *dmi;
-
-               /* Need to hash on the multicast address. */
-               for (dmi = dev->mc_list; dmi; dmi = dmi->next) {
-                       unsigned long mc_crc;
-                       unsigned int bit_number;
-
-                       mc_crc = ether_crc(6, (char *)dmi->dmi_addr);
-                       bit_number = 63 - (mc_crc >> 26);       /* MSB: 0 LSB: 63 */
-                       em0gaht[bit_number >> 4] |=
-                           0x8000 >> (bit_number & 0x0f);
-               }
-               emacp->em0gaht1 = em0gaht[0];
-               emacp->em0gaht2 = em0gaht[1];
-               emacp->em0gaht3 = em0gaht[2];
-               emacp->em0gaht4 = em0gaht[3];
+       return emac_xmit_finish(dev, skb->len);
 
-               /* Turn on multicast addressing */
-               rmr |= EMAC_RMR_MAE;
+      undo_frame:
+       /* Well, too bad. Our previous estimation was overly optimistic. 
+        * Undo everything.
+        */
+       while (slot != dev->tx_slot) {
+               dev->tx_desc[slot].ctrl = 0;
+               --dev->tx_cnt;
+               if (--slot < 0)
+                       slot = NUM_TX_BUFF - 1;
        }
-       out_be32(&emacp->em0rmr, rmr);
+       ++dev->estats.tx_undo;
+
+      stop_queue:
+       netif_stop_queue(ndev);
+       DBG2("%d: stopped TX queue" NL, dev->def->index);
+       return 1;
 }
+#else
+# define emac_start_xmit_sg    emac_start_xmit
+#endif /* !defined(CONFIG_IBM_EMAC_TAH) */
 
-static int emac_init_tah(struct ocp_enet_private *fep)
+/* BHs disabled */
+static void emac_parse_tx_error(struct ocp_enet_private *dev, u16 ctrl)
 {
-       tah_t *tahp;
+       struct ibm_emac_error_stats *st = &dev->estats;
+       DBG("%d: BD TX error %04x" NL, dev->def->index, ctrl);
+
+       ++st->tx_bd_errors;
+       if (ctrl & EMAC_TX_ST_BFCS)
+               ++st->tx_bd_bad_fcs;
+       if (ctrl & EMAC_TX_ST_LCS)
+               ++st->tx_bd_carrier_loss;
+       if (ctrl & EMAC_TX_ST_ED)
+               ++st->tx_bd_excessive_deferral;
+       if (ctrl & EMAC_TX_ST_EC)
+               ++st->tx_bd_excessive_collisions;
+       if (ctrl & EMAC_TX_ST_LC)
+               ++st->tx_bd_late_collision;
+       if (ctrl & EMAC_TX_ST_MC)
+               ++st->tx_bd_multple_collisions;
+       if (ctrl & EMAC_TX_ST_SC)
+               ++st->tx_bd_single_collision;
+       if (ctrl & EMAC_TX_ST_UR)
+               ++st->tx_bd_underrun;
+       if (ctrl & EMAC_TX_ST_SQE)
+               ++st->tx_bd_sqe;
+}
 
-       /* Initialize TAH and enable checksum verification */
-       tahp = (tah_t *) ioremap(fep->tah_dev->def->paddr, sizeof(*tahp));
+static void emac_poll_tx(void *param)
+{
+       struct ocp_enet_private *dev = param;
+       DBG2("%d: poll_tx, %d %d" NL, dev->def->index, dev->tx_cnt,
+            dev->ack_slot);
+
+       if (dev->tx_cnt) {
+               u16 ctrl;
+               int slot = dev->ack_slot, n = 0;
+             again:
+               ctrl = dev->tx_desc[slot].ctrl;
+               if (!(ctrl & MAL_TX_CTRL_READY)) {
+                       struct sk_buff *skb = dev->tx_skb[slot];
+                       ++n;
+
+                       if (skb) {
+                               dev_kfree_skb(skb);
+                               dev->tx_skb[slot] = NULL;
+                       }
+                       slot = (slot + 1) % NUM_TX_BUFF;
 
-       if (tahp == NULL) {
-               printk(KERN_ERR "tah%d: Cannot ioremap TAH registers!\n",
-                      fep->tah_dev->def->index);
+                       if (unlikely(EMAC_IS_BAD_TX(ctrl)))
+                               emac_parse_tx_error(dev, ctrl);
 
-               return -ENOMEM;
-       }
-
-       out_be32(&tahp->tah_mr, TAH_MR_SR);
+                       if (--dev->tx_cnt)
+                               goto again;
+               }
+               if (n) {
+                       dev->ack_slot = slot;
+                       if (netif_queue_stopped(dev->ndev) &&
+                           dev->tx_cnt < EMAC_TX_WAKEUP_THRESH)
+                               netif_wake_queue(dev->ndev);
 
-       /* wait for reset to complete */
-       while (in_be32(&tahp->tah_mr) & TAH_MR_SR) ;
+                       DBG2("%d: tx %d pkts" NL, dev->def->index, n);
+               }
+       }
+}
 
-       /* 10KB TAH TX FIFO accomodates the max MTU of 9000 */
-       out_be32(&tahp->tah_mr,
-                TAH_MR_CVR | TAH_MR_ST_768 | TAH_MR_TFS_10KB | TAH_MR_DTFP |
-                TAH_MR_DIG);
+static inline void emac_recycle_rx_skb(struct ocp_enet_private *dev, int slot,
+                                      int len)
+{
+       struct sk_buff *skb = dev->rx_skb[slot];
+       DBG2("%d: recycle %d %d" NL, dev->def->index, slot, len);
 
-       iounmap(tahp);
+       if (len) 
+               dma_map_single(dev->ldev, skb->data - 2, 
+                              EMAC_DMA_ALIGN(len + 2), DMA_FROM_DEVICE);
 
-       return 0;
+       dev->rx_desc[slot].data_len = 0;
+       barrier();
+       dev->rx_desc[slot].ctrl = MAL_RX_CTRL_EMPTY |
+           (slot == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
 }
 
-static void emac_init_rings(struct net_device *dev)
+static void emac_parse_rx_error(struct ocp_enet_private *dev, u16 ctrl)
 {
-       struct ocp_enet_private *ep = dev->priv;
-       int loop;
+       struct ibm_emac_error_stats *st = &dev->estats;
+       DBG("%d: BD RX error %04x" NL, dev->def->index, ctrl);
+
+       ++st->rx_bd_errors;
+       if (ctrl & EMAC_RX_ST_OE)
+               ++st->rx_bd_overrun;
+       if (ctrl & EMAC_RX_ST_BP)
+               ++st->rx_bd_bad_packet;
+       if (ctrl & EMAC_RX_ST_RP)
+               ++st->rx_bd_runt_packet;
+       if (ctrl & EMAC_RX_ST_SE)
+               ++st->rx_bd_short_event;
+       if (ctrl & EMAC_RX_ST_AE)
+               ++st->rx_bd_alignment_error;
+       if (ctrl & EMAC_RX_ST_BFCS)
+               ++st->rx_bd_bad_fcs;
+       if (ctrl & EMAC_RX_ST_PTL)
+               ++st->rx_bd_packet_too_long;
+       if (ctrl & EMAC_RX_ST_ORE)
+               ++st->rx_bd_out_of_range;
+       if (ctrl & EMAC_RX_ST_IRE)
+               ++st->rx_bd_in_range;
+}
 
-       ep->tx_desc = (struct mal_descriptor *)((char *)ep->mal->tx_virt_addr +
-                                               (ep->mal_tx_chan *
-                                                MAL_DT_ALIGN));
-       ep->rx_desc =
-           (struct mal_descriptor *)((char *)ep->mal->rx_virt_addr +
-                                     (ep->mal_rx_chan * MAL_DT_ALIGN));
+static inline void emac_rx_csum(struct ocp_enet_private *dev,
+                               struct sk_buff *skb, u16 ctrl)
+{
+#if defined(CONFIG_IBM_EMAC_TAH)
+       if (!ctrl && dev->tah_dev) {
+               skb->ip_summed = CHECKSUM_UNNECESSARY;
+               ++dev->stats.rx_packets_csum;
+       }
+#endif
+}
 
-       /* Fill in the transmit descriptor ring. */
-       for (loop = 0; loop < NUM_TX_BUFF; loop++) {
-               if (ep->tx_skb[loop]) {
-                       dma_unmap_single(&ep->ocpdev->dev,
-                                        ep->tx_desc[loop].data_ptr,
-                                        ep->tx_desc[loop].data_len,
-                                        DMA_TO_DEVICE);
-                       dev_kfree_skb_irq(ep->tx_skb[loop]);
+static inline int emac_rx_sg_append(struct ocp_enet_private *dev, int slot)
+{
+       if (likely(dev->rx_sg_skb != NULL)) {
+               int len = dev->rx_desc[slot].data_len;
+               int tot_len = dev->rx_sg_skb->len + len;
+
+               if (unlikely(tot_len + 2 > dev->rx_skb_size)) {
+                       ++dev->estats.rx_dropped_mtu;
+                       dev_kfree_skb(dev->rx_sg_skb);
+                       dev->rx_sg_skb = NULL;
+               } else {
+                       cacheable_memcpy(dev->rx_sg_skb->tail,
+                                        dev->rx_skb[slot]->data, len);
+                       skb_put(dev->rx_sg_skb, len);
+                       emac_recycle_rx_skb(dev, slot, len);
+                       return 0;
                }
-               ep->tx_skb[loop] = NULL;
-               ep->tx_desc[loop].ctrl = 0;
-               ep->tx_desc[loop].data_len = 0;
-               ep->tx_desc[loop].data_ptr = NULL;
-       }
-       ep->tx_desc[loop - 1].ctrl |= MAL_TX_CTRL_WRAP;
-
-       /* Format the receive descriptor ring. */
-       ep->rx_slot = 0;
-       /* Default is MTU=1500 + Ethernet overhead */
-       ep->rx_buffer_size = dev->mtu + ENET_HEADER_SIZE + ENET_FCS_SIZE;
-       emac_rx_fill(dev, 0);
-       if (ep->rx_slot != 0) {
-               printk(KERN_ERR
-                      "%s: Not enough mem for RxChain durning Open?\n",
-                      dev->name);
-               /*We couldn't fill the ring at startup?
-                *We could clean up and fail to open but right now we will try to
-                *carry on. It may be a sign of a bad NUM_RX_BUFF value
-                */
        }
-
-       ep->tx_cnt = 0;
-       ep->tx_slot = 0;
-       ep->ack_slot = 0;
+       emac_recycle_rx_skb(dev, slot, 0);
+       return -1;
 }
 
-static void emac_reset_configure(struct ocp_enet_private *fep)
+/* BHs disabled */
+static int emac_poll_rx(void *param, int budget)
 {
-       emac_t *emacp = fep->emacp;
-       int i;
-
-       mal_disable_tx_channels(fep->mal, fep->commac.tx_chan_mask);
-       mal_disable_rx_channels(fep->mal, fep->commac.rx_chan_mask);
+       struct ocp_enet_private *dev = param;
+       int slot = dev->rx_slot, received = 0;
 
-       /*
-        * Check for a link, some PHYs don't provide a clock if
-        * no link is present.  Some EMACs will not come out of
-        * soft reset without a PHY clock present.
-        */
-       if (fep->phy_mii.def->ops->poll_link(&fep->phy_mii)) {
-               /* Reset the EMAC */
-               out_be32(&emacp->em0mr0, EMAC_M0_SRST);
-               udelay(20);
-               for (i = 0; i < 100; i++) {
-                       if ((in_be32(&emacp->em0mr0) & EMAC_M0_SRST) == 0)
-                               break;
-                       udelay(10);
-               }
-
-               if (i >= 100) {
-                       printk(KERN_ERR "%s: Cannot reset EMAC\n",
-                              fep->ndev->name);
-                       return;
-               }
-       }
+       DBG2("%d: poll_rx(%d)" NL, dev->def->index, budget);
 
-       /* Switch IRQs off for now */
-       out_be32(&emacp->em0iser, 0);
+      again:
+       while (budget > 0) {
+               int len;
+               struct sk_buff *skb;
+               u16 ctrl = dev->rx_desc[slot].ctrl;
 
-       /* Configure MAL rx channel */
-       mal_set_rcbs(fep->mal, fep->mal_rx_chan, DESC_BUF_SIZE_REG);
+               if (ctrl & MAL_RX_CTRL_EMPTY)
+                       break;
 
-       /* set the high address */
-       out_be32(&emacp->em0iahr,
-                (fep->ndev->dev_addr[0] << 8) | fep->ndev->dev_addr[1]);
+               skb = dev->rx_skb[slot];
+               barrier();
+               len = dev->rx_desc[slot].data_len;
 
-       /* set the low address */
-       out_be32(&emacp->em0ialr,
-                (fep->ndev->dev_addr[2] << 24) | (fep->ndev->dev_addr[3] << 16)
-                | (fep->ndev->dev_addr[4] << 8) | fep->ndev->dev_addr[5]);
+               if (unlikely(!MAL_IS_SINGLE_RX(ctrl)))
+                       goto sg;
 
-       /* Adjust to link */
-       if (netif_carrier_ok(fep->ndev))
-               emac_adjust_to_link(fep);
+               ctrl &= EMAC_BAD_RX_MASK;
+               if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
+                       emac_parse_rx_error(dev, ctrl);
+                       ++dev->estats.rx_dropped_error;
+                       emac_recycle_rx_skb(dev, slot, 0);
+                       len = 0;
+                       goto next;
+               }
 
-       /* enable broadcast/individual address and RX FIFO defaults */
-       out_be32(&emacp->em0rmr, EMAC_RMR_DEFAULT);
+               if (len && len < EMAC_RX_COPY_THRESH) {
+                       struct sk_buff *copy_skb =
+                           alloc_skb(len + EMAC_RX_SKB_HEADROOM + 2, GFP_ATOMIC);
+                       if (unlikely(!copy_skb))
+                               goto oom;
+
+                       skb_reserve(copy_skb, EMAC_RX_SKB_HEADROOM + 2);
+                       cacheable_memcpy(copy_skb->data - 2, skb->data - 2,
+                                        len + 2);
+                       emac_recycle_rx_skb(dev, slot, len);
+                       skb = copy_skb;
+               } else if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC)))
+                       goto oom;
+
+               skb_put(skb, len);
+             push_packet:
+               skb->dev = dev->ndev;
+               skb->protocol = eth_type_trans(skb, dev->ndev);
+               emac_rx_csum(dev, skb, ctrl);
+
+               if (unlikely(netif_receive_skb(skb) == NET_RX_DROP))
+                       ++dev->estats.rx_dropped_stack;
+             next:
+               ++dev->stats.rx_packets;
+             skip:
+               dev->stats.rx_bytes += len;
+               slot = (slot + 1) % NUM_RX_BUFF;
+               --budget;
+               ++received;
+               continue;
+             sg:
+               if (ctrl & MAL_RX_CTRL_FIRST) {
+                       BUG_ON(dev->rx_sg_skb);
+                       if (unlikely(emac_alloc_rx_skb(dev, slot, GFP_ATOMIC))) {
+                               DBG("%d: rx OOM %d" NL, dev->def->index, slot);
+                               ++dev->estats.rx_dropped_oom;
+                               emac_recycle_rx_skb(dev, slot, 0);
+                       } else {
+                               dev->rx_sg_skb = skb;
+                               skb_put(skb, len);
+                       }
+               } else if (!emac_rx_sg_append(dev, slot) &&
+                          (ctrl & MAL_RX_CTRL_LAST)) {
+
+                       skb = dev->rx_sg_skb;
+                       dev->rx_sg_skb = NULL;
+
+                       ctrl &= EMAC_BAD_RX_MASK;
+                       if (unlikely(ctrl && ctrl != EMAC_RX_TAH_BAD_CSUM)) {
+                               emac_parse_rx_error(dev, ctrl);
+                               ++dev->estats.rx_dropped_error;
+                               dev_kfree_skb(skb);
+                               len = 0;
+                       } else
+                               goto push_packet;
+               }
+               goto skip;
+             oom:
+               DBG("%d: rx OOM %d" NL, dev->def->index, slot);
+               /* Drop the packet and recycle skb */
+               ++dev->estats.rx_dropped_oom;
+               emac_recycle_rx_skb(dev, slot, 0);
+               goto next;
+       }
 
-       /* set transmit request threshold register */
-       out_be32(&emacp->em0trtr, EMAC_TRTR_DEFAULT);
+       if (received) {
+               DBG2("%d: rx %d BDs" NL, dev->def->index, received);
+               dev->rx_slot = slot;
+       }
 
-       /* Reconfigure multicast */
-       __emac_set_multicast_list(fep->ndev);
+       if (unlikely(budget && dev->commac.rx_stopped)) {
+               struct ocp_func_emac_data *emacdata = dev->def->additions;
 
-       /* Set receiver/transmitter defaults */
-       out_be32(&emacp->em0rwmr, EMAC_RWMR_DEFAULT);
-       out_be32(&emacp->em0tmr0, EMAC_TMR0_DEFAULT);
-       out_be32(&emacp->em0tmr1, EMAC_TMR1_DEFAULT);
+               barrier();
+               if (!(dev->rx_desc[slot].ctrl & MAL_RX_CTRL_EMPTY)) {
+                       DBG2("%d: rx restart" NL, dev->def->index);
+                       received = 0;
+                       goto again;
+               }
 
-       /* set frame gap */
-       out_be32(&emacp->em0ipgvr, CONFIG_IBM_EMAC_FGAP);
-       
-       /* set VLAN Tag Protocol Identifier */
-       out_be32(&emacp->em0vtpid, 0x8100);
+               if (dev->rx_sg_skb) {
+                       DBG2("%d: dropping partial rx packet" NL,
+                            dev->def->index);
+                       ++dev->estats.rx_dropped_error;
+                       dev_kfree_skb(dev->rx_sg_skb);
+                       dev->rx_sg_skb = NULL;
+               }
 
-       /* Init ring buffers */
-       emac_init_rings(fep->ndev);
+               dev->commac.rx_stopped = 0;
+               mal_enable_rx_channel(dev->mal, emacdata->mal_rx_chan);
+               emac_rx_enable(dev);
+               dev->rx_slot = 0;
+       }
+       return received;
 }
 
-static void emac_kick(struct ocp_enet_private *fep)
+/* BHs disabled */
+static int emac_peek_rx(void *param)
 {
-       emac_t *emacp = fep->emacp;
-       unsigned long emac_ier;
-
-       emac_ier = EMAC_ISR_PP | EMAC_ISR_BP | EMAC_ISR_RP |
-           EMAC_ISR_SE | EMAC_ISR_PTLE | EMAC_ISR_ALE |
-           EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
+       struct ocp_enet_private *dev = param;
+       return !(dev->rx_desc[dev->rx_slot].ctrl & MAL_RX_CTRL_EMPTY);
+}
 
-       out_be32(&emacp->em0iser, emac_ier);
+/* BHs disabled */
+static int emac_peek_rx_sg(void *param)
+{
+       struct ocp_enet_private *dev = param;
+       int slot = dev->rx_slot;
+       while (1) {
+               u16 ctrl = dev->rx_desc[slot].ctrl;
+               if (ctrl & MAL_RX_CTRL_EMPTY)
+                       return 0;
+               else if (ctrl & MAL_RX_CTRL_LAST)
+                       return 1;
 
-       /* enable all MAL transmit and receive channels */
-       mal_enable_tx_channels(fep->mal, fep->commac.tx_chan_mask);
-       mal_enable_rx_channels(fep->mal, fep->commac.rx_chan_mask);
+               slot = (slot + 1) % NUM_RX_BUFF;
 
-       /* set transmit and receive enable */
-       out_be32(&emacp->em0mr0, EMAC_M0_TXE | EMAC_M0_RXE);
+               /* I'm just being paranoid here :) */
+               if (unlikely(slot == dev->rx_slot))
+                       return 0;
+       }
 }
 
-static void
-emac_start_link(struct ocp_enet_private *fep, struct ethtool_cmd *ep)
+/* Hard IRQ */
+static void emac_rxde(void *param)
 {
-       u32 advertise;
-       int autoneg;
-       int forced_speed;
-       int forced_duplex;
+       struct ocp_enet_private *dev = param;
+       ++dev->estats.rx_stopped;
+       emac_rx_disable_async(dev);
+}
 
-       /* Default advertise */
-       advertise = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
-           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
-           ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full;
-       autoneg = fep->want_autoneg;
-       forced_speed = fep->phy_mii.speed;
-       forced_duplex = fep->phy_mii.duplex;
+/* Hard IRQ */
+static irqreturn_t emac_irq(int irq, void *dev_instance, struct pt_regs *regs)
+{
+       struct ocp_enet_private *dev = dev_instance;
+       struct emac_regs *p = dev->emacp;
+       struct ibm_emac_error_stats *st = &dev->estats;
+
+       u32 isr = in_be32(&p->isr);
+       out_be32(&p->isr, isr);
+
+       DBG("%d: isr = %08x" NL, dev->def->index, isr);
+
+       if (isr & EMAC_ISR_TXPE)
+               ++st->tx_parity;
+       if (isr & EMAC_ISR_RXPE)
+               ++st->rx_parity;
+       if (isr & EMAC_ISR_TXUE)
+               ++st->tx_underrun;
+       if (isr & EMAC_ISR_RXOE)
+               ++st->rx_fifo_overrun;
+       if (isr & EMAC_ISR_OVR)
+               ++st->rx_overrun;
+       if (isr & EMAC_ISR_BP)
+               ++st->rx_bad_packet;
+       if (isr & EMAC_ISR_RP)
+               ++st->rx_runt_packet;
+       if (isr & EMAC_ISR_SE)
+               ++st->rx_short_event;
+       if (isr & EMAC_ISR_ALE)
+               ++st->rx_alignment_error;
+       if (isr & EMAC_ISR_BFCS)
+               ++st->rx_bad_fcs;
+       if (isr & EMAC_ISR_PTLE)
+               ++st->rx_packet_too_long;
+       if (isr & EMAC_ISR_ORE)
+               ++st->rx_out_of_range;
+       if (isr & EMAC_ISR_IRE)
+               ++st->rx_in_range;
+       if (isr & EMAC_ISR_SQE)
+               ++st->tx_sqe;
+       if (isr & EMAC_ISR_TE)
+               ++st->tx_errors;
 
-       /* Setup link parameters */
-       if (ep) {
-               if (ep->autoneg == AUTONEG_ENABLE) {
-                       advertise = ep->advertising;
-                       autoneg = 1;
-               } else {
-                       autoneg = 0;
-                       forced_speed = ep->speed;
-                       forced_duplex = ep->duplex;
-               }
-       }
+       return IRQ_HANDLED;
+}
 
-       /* Configure PHY & start aneg */
-       fep->want_autoneg = autoneg;
-       if (autoneg) {
-               LINK_DEBUG(("%s: start link aneg, advertise: 0x%x\n",
-                           fep->ndev->name, advertise));
-               fep->phy_mii.def->ops->setup_aneg(&fep->phy_mii, advertise);
-       } else {
-               LINK_DEBUG(("%s: start link forced, speed: %d, duplex: %d\n",
-                           fep->ndev->name, forced_speed, forced_duplex));
-               fep->phy_mii.def->ops->setup_forced(&fep->phy_mii, forced_speed,
-                                                   forced_duplex);
-       }
-       fep->timer_ticks = 0;
-       mod_timer(&fep->link_timer, jiffies + HZ);
+static struct net_device_stats *emac_stats(struct net_device *ndev)
+{
+       struct ocp_enet_private *dev = ndev->priv;
+       struct ibm_emac_stats *st = &dev->stats;
+       struct ibm_emac_error_stats *est = &dev->estats;
+       struct net_device_stats *nst = &dev->nstats;
+
+       DBG2("%d: stats" NL, dev->def->index);
+
+       /* Compute "legacy" statistics */
+       local_irq_disable();
+       nst->rx_packets = (unsigned long)st->rx_packets;
+       nst->rx_bytes = (unsigned long)st->rx_bytes;
+       nst->tx_packets = (unsigned long)st->tx_packets;
+       nst->tx_bytes = (unsigned long)st->tx_bytes;
+       nst->rx_dropped = (unsigned long)(est->rx_dropped_oom +
+                                         est->rx_dropped_error +
+                                         est->rx_dropped_resize +
+                                         est->rx_dropped_mtu);
+       nst->tx_dropped = (unsigned long)est->tx_dropped;
+
+       nst->rx_errors = (unsigned long)est->rx_bd_errors;
+       nst->rx_fifo_errors = (unsigned long)(est->rx_bd_overrun +
+                                             est->rx_fifo_overrun +
+                                             est->rx_overrun);
+       nst->rx_frame_errors = (unsigned long)(est->rx_bd_alignment_error +
+                                              est->rx_alignment_error);
+       nst->rx_crc_errors = (unsigned long)(est->rx_bd_bad_fcs +
+                                            est->rx_bad_fcs);
+       nst->rx_length_errors = (unsigned long)(est->rx_bd_runt_packet +
+                                               est->rx_bd_short_event +
+                                               est->rx_bd_packet_too_long +
+                                               est->rx_bd_out_of_range +
+                                               est->rx_bd_in_range +
+                                               est->rx_runt_packet +
+                                               est->rx_short_event +
+                                               est->rx_packet_too_long +
+                                               est->rx_out_of_range +
+                                               est->rx_in_range);
+
+       nst->tx_errors = (unsigned long)(est->tx_bd_errors + est->tx_errors);
+       nst->tx_fifo_errors = (unsigned long)(est->tx_bd_underrun +
+                                             est->tx_underrun);
+       nst->tx_carrier_errors = (unsigned long)est->tx_bd_carrier_loss;
+       nst->collisions = (unsigned long)(est->tx_bd_excessive_deferral +
+                                         est->tx_bd_excessive_collisions +
+                                         est->tx_bd_late_collision +
+                                         est->tx_bd_multple_collisions);
+       local_irq_enable();
+       return nst;
 }
 
-static void emac_link_timer(unsigned long data)
+static void emac_remove(struct ocp_device *ocpdev)
 {
-       struct ocp_enet_private *fep = (struct ocp_enet_private *)data;
-       int link;
+       struct ocp_enet_private *dev = ocp_get_drvdata(ocpdev);
 
-       if (fep->going_away)
-               return;
+       DBG("%d: remove" NL, dev->def->index);
 
-       spin_lock_irq(&fep->lock);
+       ocp_set_drvdata(ocpdev, 0);
+       unregister_netdev(dev->ndev);
 
-       link = fep->phy_mii.def->ops->poll_link(&fep->phy_mii);
-       LINK_DEBUG(("%s: poll_link: %d\n", fep->ndev->name, link));
+       tah_fini(dev->tah_dev);
+       rgmii_fini(dev->rgmii_dev, dev->rgmii_input);
+       zmii_fini(dev->zmii_dev, dev->zmii_input);
 
-       if (link == netif_carrier_ok(fep->ndev)) {
-               if (!link && fep->want_autoneg && (++fep->timer_ticks) > 10)
-                       emac_start_link(fep, NULL);
-               goto out;
-       }
-       printk(KERN_INFO "%s: Link is %s\n", fep->ndev->name,
-              link ? "Up" : "Down");
-       if (link) {
-               netif_carrier_on(fep->ndev);
-               /* Chip needs a full reset on config change. That sucks, so I
-                * should ultimately move that to some tasklet to limit
-                * latency peaks caused by this code
-                */
-               emac_reset_configure(fep);
-               if (fep->opened)
-                       emac_kick(fep);
-       } else {
-               fep->timer_ticks = 0;
-               netif_carrier_off(fep->ndev);
-       }
-      out:
-       mod_timer(&fep->link_timer, jiffies + HZ);
-       spin_unlock_irq(&fep->lock);
+       emac_dbg_register(dev->def->index, 0);
+
+       mal_unregister_commac(dev->mal, &dev->commac);
+       iounmap((void *)dev->emacp);
+       kfree(dev->ndev);
 }
 
-static void emac_set_multicast_list(struct net_device *dev)
-{
-       struct ocp_enet_private *fep = dev->priv;
+static struct mal_commac_ops emac_commac_ops = {
+       .poll_tx = &emac_poll_tx,
+       .poll_rx = &emac_poll_rx,
+       .peek_rx = &emac_peek_rx,
+       .rxde = &emac_rxde,
+};
 
-       spin_lock_irq(&