ARM: tegra11: Set up tegra timer as clock source
Bo Yan [Tue, 17 Jul 2012 06:23:45 +0000 (23:23 -0700)]
architected timer is set up for boot cpu in percpu_timer_setup, this
is quite late during system boot. Before it's done, it is necessary
to register clockevents using tegra timer.

The same thing is also true for ARM twd timer, which is already taken
care of in the code. This change merely enables the same code for
arch timer.

Change-Id: I2ffd1ffa9be8b71902cb6151462d5b6cb641a355
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/116349
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

arch/arm/mach-tegra/timer.c

index dc92138..0e42f18 100644 (file)
@@ -580,37 +580,36 @@ void __init tegra_init_timer(void)
        /* Architectural timers take precedence over broadcast timers.
           Only register a broadcast clockevent device if architectural
           timers do not exist or cannot be initialized. */
-       if (tegra_init_arch_timer()) {
+       if (tegra_init_arch_timer())
                /* Architectural timers do not exist or cannot be initialzied.
                   Fall back to using the broadcast timer as the sched clock. */
                setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
 
-               ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
-                       "timer_us", 1000000, 300, 32,
-                       clocksource_mmio_readl_up);
-               if (ret) {
-                       pr_err("%s: Failed to register clocksource: %d\n",
-                               __func__, ret);
-                       BUG();
-               }
-
-               ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
-               if (ret) {
-                       pr_err("%s: Failed to register timer IRQ: %d\n",
-                               __func__, ret);
-                       BUG();
-               }
+       ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
+               "timer_us", 1000000, 300, 32,
+               clocksource_mmio_readl_up);
+       if (ret) {
+               pr_err("%s: Failed to register clocksource: %d\n",
+                       __func__, ret);
+               BUG();
+       }
 
-               clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
-               tegra_clockevent.max_delta_ns =
-                       clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
-               tegra_clockevent.min_delta_ns =
-                       clockevent_delta2ns(0x1, &tegra_clockevent);
-               tegra_clockevent.cpumask = cpu_all_mask;
-               tegra_clockevent.irq = tegra_timer_irq.irq;
-               clockevents_register_device(&tegra_clockevent);
+       ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
+       if (ret) {
+               pr_err("%s: Failed to register timer IRQ: %d\n",
+                       __func__, ret);
+               BUG();
        }
 
+       clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
+       tegra_clockevent.max_delta_ns =
+               clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
+       tegra_clockevent.min_delta_ns =
+               clockevent_delta2ns(0x1, &tegra_clockevent);
+       tegra_clockevent.cpumask = cpu_all_mask;
+       tegra_clockevent.irq = tegra_timer_irq.irq;
+       clockevents_register_device(&tegra_clockevent);
+
        register_syscore_ops(&tegra_timer_syscore_ops);
        late_time_init = tegra_init_late_timer;
 }