ath5k: read eeprom IQ calibration values correctly for G mode
Bruno Randolf [Tue, 9 Mar 2010 07:56:10 +0000 (16:56 +0900)]
we read the IQ correction values (i_cal and q_cal) for G mode from a wrong
location (the same shifts as for A mode is applied which is incorrect). use
correct locations, matching the docs and HAL sources.

also we should write IQ correction only when we have that information in the
EEPROM, starting from version 4. also write it in the same way as we do in the
periodic recalibration (enable last), just to be sure.

Signed-off-by: Bruno Randolf <br1@einfach.org>
Acked-by: Nick Kossifidis <mickflemm@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

drivers/net/wireless/ath/ath5k/eeprom.c
drivers/net/wireless/ath/ath5k/reset.c

index 6a3f4da..10b5226 100644 (file)
@@ -429,8 +429,8 @@ static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
                        ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
 
                AR5K_EEPROM_READ(o++, val);
-               ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
-               ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
+               ee->ee_i_cal[mode] = (val >> 5) & 0x3f;
+               ee->ee_q_cal[mode] = val & 0x1f;
 
                if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
                        AR5K_EEPROM_READ(o++, val);
index c780b55..cbf28e3 100644 (file)
@@ -851,12 +851,15 @@ static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
                                AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
                                AR5K_INIT_CYCRSSI_THR1);
 
-       /* I/Q correction
-        * TODO: Per channel i/q infos ? */
-       AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
-               AR5K_PHY_IQ_CORR_ENABLE |
-               (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) |
-               ee->ee_q_cal[ee_mode]);
+       /* I/Q correction (set enable bit last to match HAL sources) */
+       /* TODO: Per channel i/q infos ? */
+       if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
+               AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF,
+                           ee->ee_i_cal[ee_mode]);
+               AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF,
+                           ee->ee_q_cal[ee_mode]);
+               AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
+       }
 
        /* Heavy clipping -disable for now */
        if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)