drm/radeon: use DSTCACHE_CTLSTAT rather than RB2D_DSTCACHE_CTLSTAT
Alex Deucher [Thu, 19 Jun 2008 02:39:23 +0000 (12:39 +1000)]
According to the hw guys, you should use DSTCACHE_CTLSTAT to flush
the 2D dst cache rather than RB2D_DSTCACHE_CTLSTAT.

Signed-off-by: Dave Airlie <airlied@redhat.com>

drivers/char/drm/radeon_cp.c
drivers/char/drm/radeon_drv.h

index 441645e..e53158f 100644 (file)
@@ -204,12 +204,12 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
                RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp);
 
                /* 2D */
-               tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
+               tmp = RADEON_READ(R300_DSTCACHE_CTLSTAT);
                tmp |= RADEON_RB3D_DC_FLUSH_ALL;
-               RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
+               RADEON_WRITE(R300_DSTCACHE_CTLSTAT, tmp);
 
                for (i = 0; i < dev_priv->usec_timeout; i++) {
-                       if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
+                       if (!(RADEON_READ(R300_DSTCACHE_CTLSTAT)
                          & RADEON_RB3D_DC_BUSY)) {
                                return 0;
                        }
index e20b5d8..3f0eca9 100644 (file)
@@ -662,11 +662,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
 #define RADEON_PP_TXFILTER_1           0x1c6c
 #define RADEON_PP_TXFILTER_2           0x1c84
 
-#define RADEON_RB2D_DSTCACHE_CTLSTAT   0x342c
-#      define RADEON_RB2D_DC_FLUSH             (3 << 0)
-#      define RADEON_RB2D_DC_FREE              (3 << 2)
-#      define RADEON_RB2D_DC_FLUSH_ALL         0xf
-#      define RADEON_RB2D_DC_BUSY              (1 << 31)
+#define R300_RB2D_DSTCACHE_CTLSTAT     0x342c /* use R300_DSTCACHE_CTLSTAT */
+#define R300_DSTCACHE_CTLSTAT          0x1714
+#      define R300_RB2D_DC_FLUSH               (3 << 0)
+#      define R300_RB2D_DC_FREE                (3 << 2)
+#      define R300_RB2D_DC_FLUSH_ALL           0xf
+#      define R300_RB2D_DC_BUSY                (1 << 31)
 #define RADEON_RB3D_CNTL               0x1c3c
 #      define RADEON_ALPHA_BLEND_ENABLE        (1 << 0)
 #      define RADEON_PLANE_MASK_ENABLE         (1 << 1)