mmc: tegra: Fix SDR50 mode clock rate setting
Pavan Kunapuli [Wed, 9 May 2012 12:44:51 +0000 (17:44 +0530)]
In SDR50 mode, set the controller clock to double
the requested clock to ensure that the core voltage
is maintained at a min of 1.2V.

Bug 965298

Change-Id: I557a07de97efd6b44f812a11da657e03d3ddefd0
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/101522
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

drivers/mmc/host/sdhci-tegra.c

index 399ca8b..0e2605d 100644 (file)
@@ -393,8 +393,14 @@ static void tegra_sdhci_set_clk_rate(struct sdhci_host *sdhci,
        struct sdhci_tegra *tegra_host = pltfm_host->priv;
        unsigned int clk_rate;
 
+       /*
+        * In SDR50 mode, run the sdmmc controller at freq greater than
+        * 104MHz to ensure the core voltage is at 1.2V. If the core voltage
+        * is below 1.2V, CRC errors would occur during data transfers.
+        */
        if (sdhci->mmc->card &&
-               mmc_card_ddr_mode(sdhci->mmc->card)) {
+               (mmc_card_ddr_mode(sdhci->mmc->card) ||
+               (sdhci->mmc->ios.timing == MMC_TIMING_UHS_SDR50))) {
                /*
                 * In ddr mode, tegra sdmmc controller clock frequency
                 * should be double the card clock frequency.
@@ -407,15 +413,6 @@ static void tegra_sdhci_set_clk_rate(struct sdhci_host *sdhci,
                        clk_rate = tegra_sdhost_std_freq;
                else
                        clk_rate = clock;
-
-               /*
-                * In SDR50 mode, run the sdmmc controller at 208MHz to ensure
-                * the core voltage is at 1.2V. If the core voltage is below 1.2V, CRC
-                * errors would occur during data transfers.
-                */
-               if ((sdhci->mmc->ios.timing == MMC_TIMING_UHS_SDR50) &&
-                       (clk_rate == tegra_sdhost_std_freq))
-                       clk_rate <<= 1;
        }
 
        if (tegra_host->max_clk_limit &&