ALSA: hda: powergate HDA when clock gating
Jon Mayo [Fri, 7 Dec 2012 01:19:51 +0000 (17:19 -0800)]
Use powergating APIs to ensure that HDA and display play nice.
Export powergate APIs so snd-intel-hda can be built as a module.

Bug 1178366

Change-Id: I30559b9288fcbd86615a674756e70f04c9fb5d83
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/169245
Reviewed-by: Automatic_Commit_Validation_User
(cherry picked from commit ca49eeb9b0722505194635d68a7ed7a2b3a343b6)
Reviewed-on: http://git-master/r/171205

arch/arm/mach-tegra/powergate.c
drivers/video/tegra/dc/hdmi.c
sound/pci/hda/hda_intel.c

index affdf14..d338049 100644 (file)
@@ -1208,6 +1208,7 @@ err_power:
        return ret;
 #endif
 }
+EXPORT_SYMBOL(tegra_unpowergate_partition);
 
 int tegra_cpu_powergate_id(int cpuid)
 {
@@ -1570,6 +1571,7 @@ err_clk_off:
        return ret;
 #endif
 }
+EXPORT_SYMBOL(tegra_powergate_partition);
 
 int tegra_powergate_partition_with_clk_off(int id)
 {
index 37c8bb5..0b29830 100644 (file)
@@ -1426,12 +1426,14 @@ int tegra_hdmi_setup_hda_presence()
 
        if (hdmi->clk_enabled && hdmi->eld_retrieved) {
                /* If HDA_PRESENCE is already set reset it */
+               tegra_dc_unpowergate_locked(hdmi->dc);
                if (tegra_hdmi_readl(hdmi,
                                     HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0))
                        tegra_hdmi_writel(hdmi, 0,
                                     HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0);
 
                tegra_dc_hdmi_setup_eld_buff(hdmi->dc);
+               tegra_dc_powergate_locked(hdmi->dc);
                return 0;
        }
        return -ENODEV;
index 1ac4ca1..dad3a16 100644 (file)
@@ -59,6 +59,9 @@
 #ifdef CONFIG_SND_HDA_VPR
 #include <linux/nvmap.h>
 #endif
+#ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
+#include <mach/powergate.h>
+#endif
 
 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
@@ -1368,10 +1371,17 @@ static void azx_platform_enable_clocks(struct azx *chip)
 {
        int i;
 
+#ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
+#if defined(CONFIG_ARCH_TEGRA_11x_SOC)
+       tegra_unpowergate_partition(TEGRA_POWERGATE_DISB);
+#endif
+#endif
+
        for (i = 0; i < chip->platform_clk_count; i++)
                clk_enable(chip->platform_clks[i]);
 
        chip->platform_clk_enable++;
+
 }
 
 static void azx_platform_disable_clocks(struct azx *chip)
@@ -1384,6 +1394,12 @@ static void azx_platform_disable_clocks(struct azx *chip)
        for (i = 0; i < chip->platform_clk_count; i++)
                clk_disable(chip->platform_clks[i]);
 
+#ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
+#if defined(CONFIG_ARCH_TEGRA_11x_SOC)
+       tegra_powergate_partition(TEGRA_POWERGATE_DISB);
+#endif
+#endif
+
        chip->platform_clk_enable--;
 }
 #endif /* CONFIG_SND_HDA_PLATFORM_DRIVER */