ARM: tegra11: pinmux: correct SDMMC3_CLK_LB_OUT and SDMMC3_CLK_LB_IN offset
Jay Cheng [Thu, 25 Apr 2013 12:14:02 +0000 (08:14 -0400)]
Change-Id: Ia53a98a5dbf21e4a8779367edb6fba51614f02c7
Signed-off-by: Jay Cheng <jacheng@nvidia.com>
Reviewed-on: http://git-master/r/222910
Reviewed-by: Andy Park <andyp@nvidia.com>
Tested-by: Andy Park <andyp@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

arch/arm/mach-tegra/pinmux-t11-tables.c

index 864aef7..3ed6a17 100644 (file)
@@ -330,8 +330,8 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE
        PINGROUP(GPIO_W3_AUD,     PW3,          AUDIO,      SPI6,       SPI1,       SPI2,       I2C1,        SPI6,      INPUT,  0x33f0),\
        PINGROUP(USB_VBUS_EN0,    PN4,          LCD,        USB,        RSVD1,      RSVD2,      RSVD3,       RSVD1,     INPUT,  0x33f4),\
        PINGROUP(USB_VBUS_EN1,    PN5,          LCD,        USB,        RSVD1,      RSVD2,      RSVD3,       RSVD1,     INPUT,  0x33f8),\
-       PINGROUP(SDMMC3_CLK_LB_OUT,       PEE4,         SDMMC3,        SDMMC3,  RSVD1,      RSVD2,      RSVD3,       RSVD1,     INPUT,  0x33fc),\
-       PINGROUP(SDMMC3_CLK_LB_IN,        PEE5,         SDMMC3,        SDMMC3,  RSVD1,      RSVD2,      RSVD3,       RSVD1,     INPUT,  0x3400),\
+       PINGROUP(SDMMC3_CLK_LB_IN,        PEE5,         SDMMC3,        SDMMC3,  RSVD1,      RSVD2,      RSVD3,       RSVD1,     INPUT,  0x33fc),\
+       PINGROUP(SDMMC3_CLK_LB_OUT,       PEE4,         SDMMC3,        SDMMC3,  RSVD1,      RSVD2,      RSVD3,       RSVD1,     INPUT,  0x3400),\
        PINGROUP(RESET_OUT_N,     INVALID,      SYS,        RSVD0,      RSVD1,      RSVD2,      RESET_OUT_N, RSVD0,     OUTPUT, 0x3408),
 
 const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {