ARM: tegra: Set scratch1_eco register for memory dpd
Karthik Ramakrishnan [Thu, 15 Nov 2012 00:15:02 +0000 (16:15 -0800)]
Set proper memory settings for LP0 state.
Bug 1175084
Bug 1156167

Change-Id: I958af3f0dcd4805e195f6286894a011a3ed85537
Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com>
Reviewed-on: http://git-master/r/164230
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

arch/arm/mach-tegra/sleep-t3.S

index c675e91..c157dd4 100644 (file)
@@ -70,6 +70,7 @@
 
 #define PMC_IO_DPD_REQ                 0x1b8
 #define PMC_IO_DPD_STATUS              0x1bc
+#define PMC_SCRATCH1_ECO       0x264
 
 #define CLK_RESET_CCLK_BURST           0x20
 #define CLK_RESET_CCLK_DIVIDER         0x24
@@ -635,6 +636,13 @@ tegra3_cpu_clk32k:
        str     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
        ldr     r0, [r4, #PMC_SCRATCH2]
        str     r0, [r4, #PMC_PLLM_WB0_OVERRIDE]
+
+#if defined(CONFIG_ARCH_TEGRA_11x_SOC)
+       ldr r1, [r4, #PMC_SCRATCH1_ECO]
+       orr r1, r1, #0x3F
+       str r1, [r4, #PMC_SCRATCH1_ECO]
+#endif
+
        mov     pc, lr
 
 lp1_clocks_prepare: