video: tegra: dsi: fix DSI_PAD_CONTROL reg wr value on resume
Boris Suvorov [Fri, 24 Feb 2012 21:22:28 +0000 (13:22 -0800)]
In panel resume path DSI_PAD_CONTROL value gets calibrated,
however later on values are overwritten with bit settings
for ulpm mode.

refactor value for reg write to only change ulpm related bits.

Change-Id: I9f9713bdf376c06b0e1b9f43b3e6c9f719bbd855
Signed-off-by: Boris Suvorov <bsuvorov@nvidia.com>
Reviewed-on: http://git-master/r/85873
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

drivers/video/tegra/dc/dsi.c

index 2f3f630..d090846 100644 (file)
@@ -2417,10 +2417,18 @@ static void tegra_dc_dsi_enable(struct tegra_dc *dc)
                                        "DSI failed to enter ulpm\n");
                                goto fail;
                        }
-                       val = DSI_PAD_CONTROL_PAD_PDIO(0) |
+
+                       val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
+
+                       /* erase bits we're about to set */
+                       val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
+                               DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
+                               DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE));
+
+                       val |= (DSI_PAD_CONTROL_PAD_PDIO(0) |
                                DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
-                               DSI_PAD_CONTROL_PAD_PULLDN_ENAB
-                                               (TEGRA_DSI_DISABLE);
+                               DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_DISABLE));
+
                        tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
                        if (tegra_dsi_exit_ulpm(dsi) < 0) {
                                dev_err(&dc->ndev->dev,
@@ -2790,8 +2798,11 @@ static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
                }
        }
 
-       /* Suspend pad */
-       val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
+       /*
+        * Suspend pad
+        * It is ok to overwrite previous value of DSI_PAD_CONTROL reg
+        * because it will be restored properly in resume sequence
+        */
        val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
                DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
                DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);