arm: tegra: cardhu: VI_PCLK Disabling the IO reset
Laxman Dewangan [Mon, 11 Apr 2011 08:05:14 +0000 (13:05 +0530)]
Disabling the io reset for the VI_PCLK  which controls the
hdmi power enable.

bug 812083

Original-Change-Id: I1ee25a48f1bf8996a8469ff7c12d9a9f1fefa44e
Reviewed-on: http://git-master/r/27335
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Tested-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Mohit Singh <mpsingh@nvidia.com>
Tested-by: Mohit Singh <mpsingh@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I84b79ef364a64b1f21e65847eeb6fc6836e30f54

Rebase-Id: R8143d4bf216e90ec0a5affcddf0b867b76e6a44f

arch/arm/mach-tegra/board-cardhu-pinmux.c

index adfa05c..01ec5d1 100644 (file)
@@ -388,7 +388,7 @@ static __initdata struct tegra_pingroup_config cardhu_pinmux_common[] = {
        VI_PINMUX(VI_D6,           VI,              NORMAL,    NORMAL,     OUTPUT, DISABLE, DISABLE),
        VI_PINMUX(VI_D8,           SDMMC2,          NORMAL,    NORMAL,     INPUT,  DISABLE, DISABLE),
        VI_PINMUX(VI_D9,           SDMMC2,          NORMAL,    NORMAL,     INPUT,  DISABLE, DISABLE),
-       VI_PINMUX(VI_PCLK,         RSVD1,           PULL_UP,   TRISTATE,   INPUT,  DISABLE, ENABLE),
+       VI_PINMUX(VI_PCLK,         RSVD1,           PULL_UP,   TRISTATE,   INPUT,  DISABLE, DISABLE),
        VI_PINMUX(VI_HSYNC,        RSVD1,           NORMAL,    NORMAL,     INPUT,  DISABLE, DISABLE),
        VI_PINMUX(VI_VSYNC,        RSVD1,           NORMAL,    NORMAL,     INPUT,  DISABLE, DISABLE),
 };