radeon: Fix CP byte order on big endian architectures with KMS.
Michel Dänzer [Tue, 16 Jun 2009 15:29:06 +0000 (17:29 +0200)]
Signed-off-by: Dave Airlie <airlied@redhat.com>

drivers/gpu/drm/radeon/r100.c
drivers/gpu/drm/radeon/radeon_reg.h

index 8f41f70..64a692c 100644 (file)
@@ -551,6 +551,9 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
        /* cp setup */
        WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
        WREG32(RADEON_CP_RB_CNTL,
+#ifdef __BIG_ENDIAN
+              RADEON_BUF_SWAP_32BIT |
+#endif
               REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
               REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
               REG_SET(RADEON_MAX_FETCH, max_fetch) |
index 6d3d904..e1b6185 100644 (file)
 #      define RADEON_RB_BUFSZ_MASK             (0x3f << 0)
 #      define RADEON_RB_BLKSZ_SHIFT            8
 #      define RADEON_RB_BLKSZ_MASK             (0x3f << 8)
+#      define RADEON_BUF_SWAP_32BIT            (1 << 17)
 #      define RADEON_MAX_FETCH_SHIFT           18
 #      define RADEON_MAX_FETCH_MASK            (0x3 << 18)
 #      define RADEON_RB_NO_UPDATE              (1 << 27)