ARM: tegra11: clock: Do not allow 1:1.5 clock dividers ratio
Alex Frid [Thu, 25 Oct 2012 06:45:24 +0000 (23:45 -0700)]
Change-Id: Iac26d1144b45247c3b5c70a47e26a1fba228b4d0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/147680
(cherry picked from commit 723f73ae73cacb4274b2b671a8454f5741dae712)
Reviewed-on: http://git-master/r/161069
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arch/arm/mach-tegra/tegra11_clocks.c

index 6e7a63d..a7800a7 100644 (file)
 
 #define ROUND_DIVIDER_UP       0
 #define ROUND_DIVIDER_DOWN     1
+#define DIVIDER_1_5_ALLOWED    0
 
 /* PLLP default fixed rate in h/w controlled mode */
 #define PLLP_DEFAULT_FIXED_RATE                216000000
@@ -592,6 +593,10 @@ static int clk_div_x1_get_divider(unsigned long parent_rate, unsigned long rate,
        if (divider_ux1 - 2 > max_x)
                return -EINVAL;
 
+#if !DIVIDER_1_5_ALLOWED
+       if (divider_ux1 == 3)
+               divider_ux1 = (round_mode == ROUND_DIVIDER_UP) ? 4 : 2;
+#endif
        return divider_ux1 - 2;
 }