arm: tegra: raise cpu floor when display is on
Wen Yi [Wed, 22 Aug 2012 00:04:48 +0000 (17:04 -0700)]
When device is idle and display is on, the minimal
cpu frequency can drop to 51mhz. Since it takes several
tens of millisecond to ramp up cpu freq, the delay
impact negatively the performance of low latency CPU bound
tasks.

Given the power savings of several milliwatts running cpu
at 51mhz comparing to 102mhz or 204 mhz at idle, the idle
cpu freq is hence raised to 102mhz for smart panel device
and 204mhz for dump panel devices.

Bug 1036216

Change-Id: Ifb0ed88d4c5fcf5b637d09c587322cec72b8a08d
Signed-off-by: Wen Yi <wyi@nvidia.com>
(cherry picked from commit c8465feffcd0cf2401bbd6c6f535955dd68bda55)
Reviewed-on: http://git-master/r/132479
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ujjaval Patel <upatel@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

arch/arm/mach-tegra/board-cardhu-power.c
arch/arm/mach-tegra/board-enterprise-power.c
arch/arm/mach-tegra/pm.c
arch/arm/mach-tegra/pm.h

index e76cbc4..677b383 100644 (file)
@@ -1191,6 +1191,8 @@ int __init cardhu_suspend_init(void)
                        cardhu_suspend_data.lp1_core_volt_high = 0x50;
                }
 #endif
+               if (is_display_board_dsi(display_board_info.board_id))
+                       cardhu_suspend_data.cpu_wake_freq = CPU_WAKE_FREQ_LOW;
        case BOARD_PM305:
        case BOARD_PM311:
                break;
index c154841..3475452 100644 (file)
@@ -822,6 +822,7 @@ static struct tegra_suspend_platform_data enterprise_suspend_data = {
        .lp1_core_volt_low = 0x1D,
        .lp1_core_volt_high = 0x33,
 #endif
+       .cpu_wake_freq = CPU_WAKE_FREQ_LOW,
 };
 
 static void enterprise_init_deep_sleep_mode(void)
index b20b512..88dd501 100644 (file)
@@ -178,7 +178,6 @@ struct suspend_context tegra_sctx;
 #define MC_SECURITY_SIZE       0x70
 #define MC_SECURITY_CFG2       0x7c
 
-#define AWAKE_CPU_FREQ_MIN     51000
 static struct pm_qos_request_list awake_cpu_freq_req;
 
 struct dvfs_rail *tegra_cpu_rail;
@@ -1105,13 +1104,17 @@ void __init tegra_init_suspend(struct tegra_suspend_platform_data *plat)
        u32 reg;
        u32 mode;
 
+       if (plat->cpu_wake_freq == 0)
+               plat->cpu_wake_freq = CPU_WAKE_FREQ_HIGH;
+
        tegra_cpu_rail = tegra_dvfs_get_rail_by_name("vdd_cpu");
        tegra_core_rail = tegra_dvfs_get_rail_by_name("vdd_core");
        pm_qos_add_request(&awake_cpu_freq_req, PM_QOS_CPU_FREQ_MIN,
-                          AWAKE_CPU_FREQ_MIN);
+                          plat->cpu_wake_freq);
 
        tegra_pclk = clk_get_sys(NULL, "pclk");
        BUG_ON(IS_ERR(tegra_pclk));
+
        pdata = plat;
        (void)reg;
        (void)mode;
@@ -1383,7 +1386,7 @@ static void pm_late_resume(struct early_suspend *h)
 {
        if (clk_wake)
                clk_enable(clk_wake);
-       pm_qos_update_request(&awake_cpu_freq_req, (s32)AWAKE_CPU_FREQ_MIN);
+       pm_qos_update_request(&awake_cpu_freq_req, (s32)pdata->cpu_wake_freq);
 }
 
 static struct early_suspend pm_early_suspender = {
index 5ea2b7f..401c0aa 100644 (file)
 #define PMC_SCRATCH1           0x54
 #define PMC_SCRATCH4           0x60
 
+/* The following two constants are for setting the CPU freq
+ * floor when display is on. 204000Khz is for tablet and
+ * 102000KHz is for phones. The reason for different values
+ * for tablet and phone is due to phones usually have smart
+ * displays that requires less CPU activity for refreshing
+ * the screen
+ */
+
+#define CPU_WAKE_FREQ_HIGH     204000
+#define CPU_WAKE_FREQ_LOW      102000
 enum tegra_suspend_mode {
        TEGRA_SUSPEND_NONE = 0,
        TEGRA_SUSPEND_LP2,      /* CPU voltage off */
@@ -73,6 +83,7 @@ struct tegra_suspend_platform_data {
        unsigned int lp1_core_volt_low;
        unsigned int lp1_core_volt_high;
 #endif
+       int cpu_wake_freq;
 };
 
 /* clears io dpd settings before kernel code */