ARM: tegra: tegratab: Change slew rate of vdd_cpu to 2.5mV/us
Jinyoung Park [Tue, 23 Apr 2013 06:13:19 +0000 (15:13 +0900)]
Changed rate of vdd_cpu to 2.5mV/us from 5.0mV/us due to undershoot
issue when voltage down scaling.
And adjusted sample rate of cl-dvfs to 11.5kHz according to slew rate.

Bug 1268516

Change-Id: I0a613d99628361e04628682d165e1456b9635b66
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/221908
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

arch/arm/mach-tegra/board-tegratab-power.c

index b63872c..5cf36f3 100644 (file)
@@ -258,7 +258,7 @@ static struct regulator_consumer_supply palmas_regen2_supply[] = {
 };
 
 PALMAS_REGS_PDATA(smps123, 900,  1300, NULL, 0, 0, 0, 0,
-       0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0, 0);
+       0, PALMAS_EXT_CONTROL_ENABLE1, 0, 3, 0);
 PALMAS_REGS_PDATA(smps45, 900,  1400, NULL, 0, 0, 0, 0,
        0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0);
 PALMAS_REGS_PDATA(smps6, 3200,  3200, NULL, 0, 0, 1, NORMAL,
@@ -584,7 +584,7 @@ static struct tegra_suspend_platform_data tegratab_suspend_data = {
 #ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
 /* board parameters for cpu dfll */
 static struct tegra_cl_dvfs_cfg_param tegratab_cl_dvfs_param = {
-       .sample_rate = 12500,
+       .sample_rate = 11500,
 
        .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
        .cf = 10,