Blackfin arch: enable reprogram cclk and sclk for bf518f-ezbrd
Sonic Zhang [Wed, 7 Jan 2009 15:14:38 +0000 (23:14 +0800)]
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>

arch/blackfin/Kconfig
arch/blackfin/include/asm/mem_init.h

index 56ee44d..a949c4f 100644 (file)
@@ -330,6 +330,11 @@ config MEM_MT48LC32M16A2TG_75
        depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
        default y
 
+config MEM_MT48LC32M8A2_75
+       bool
+       depends on (BFIN518F_EZBRD)
+       default y
+
 source "arch/blackfin/mach-bf518/Kconfig"
 source "arch/blackfin/mach-bf527/Kconfig"
 source "arch/blackfin/mach-bf533/Kconfig"
index 3cbc0f8..255a931 100644 (file)
@@ -13,7 +13,8 @@
     defined(CONFIG_MEM_GENERIC_BOARD) || \
     defined(CONFIG_MEM_MT48LC32M8A2_75) || \
     defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
-    defined(CONFIG_MEM_MT48LC32M16A2TG_75)
+    defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
+    defined(CONFIG_MEM_MT48LC32M8A2_75)
 #if (CONFIG_SCLK_HZ > 119402985)
 #define SDRAM_tRP       TRP_2
 #define SDRAM_tRP_num   2
     defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
     defined(CONFIG_MEM_GENERIC_BOARD) || \
     defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
-    defined(CONFIG_MEM_MT48LC16M16A2TG_75)
+    defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
+    defined(CONFIG_MEM_MT48LC32M8A2_75)
   /*SDRAM INFORMATION: */
 #define SDRAM_Tref  64         /* Refresh period in milliseconds   */
 #define SDRAM_NRA   8192       /* Number of row addresses in SDRAM */