p1852: clocks: remove duplicate host1x clock limit
Nirav Patel [Tue, 5 Jun 2012 23:00:34 +0000 (16:00 -0700)]
host1x clock limit is already imposed by tegra3_dvfs.c and need not
to be explicitly set for p1852 SKU. Hence, removing the clock limit
duplication.

Bug 925358

Change-Id: I5e936f46ad64b0335561e321d61c4e8b13d7f765
Reviewed-on: http://git-master/r/106637
(cherry picked from commit ccaa3515121b637ce3870bf73f2402846670b63c)
Signed-off-by: Nirav Patel <nipatel@nvidia.com>
Reviewed-on: http://git-master/r/118130
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

arch/arm/mach-tegra/board-p1852.c

index 008b8ad..b0a593f 100644 (file)
@@ -97,7 +97,6 @@ static __initdata struct tegra_clk_init_table p1852_clk_init_table[] = {
        { "vi",                 "pll_p",        470000000,      false},
        { "vi_sensor",          "pll_p",        150000000,      false},
        { "vde",                "pll_c",        484000000,      true},
-       { "host1x",             "pll_c",        242000000,      true},
        { "mpe",                "pll_c",        484000000,      true},
        { "se",                 "pll_m",        625000000,      true},
        { "i2c1",               "pll_p",        3200000,        true},