ARM: tegra: cardhu: Separate LPDDR2 processor board
Alex Frid [Wed, 20 Apr 2011 02:01:33 +0000 (19:01 -0700)]
Made sure default DDR3 EMC DFS table is not applied to cardhu
processor board with LPDDR2.

Original-Change-Id: I78bb2a4f80a5db00e04cb82c530924219e6baa78
Reviewed-on: http://git-master/r/30311
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>

Rebase-Id: Rc526c375fd15719b434694d7db8b91099a220c2a

arch/arm/mach-tegra/board-cardhu-memory.c

index 0e95179..d654858 100644 (file)
@@ -19,6 +19,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
+#include "board.h"
 #include "board-cardhu.h"
 #include "tegra3_emc.h"
 
@@ -608,7 +609,18 @@ static const struct tegra_emc_table cardhu_emc_tables_h5tc2g[] = {
 
 int cardhu_emc_init(void)
 {
-       tegra_init_emc(cardhu_emc_tables_h5tc2g,
-               ARRAY_SIZE(cardhu_emc_tables_h5tc2g));
+       struct board_info board;
+
+       tegra_get_board_info(&board);
+
+       switch (board.board_id) {
+       case BOARD_PM269:       /* LPDDR2 table is not ready, yet */
+               break;
+       default:
+               tegra_init_emc(cardhu_emc_tables_h5tc2g,
+                       ARRAY_SIZE(cardhu_emc_tables_h5tc2g));
+               break;
+       }
+
        return 0;
 }