tegra: dc: Make data output along with pixel clock.
Roger Hsieh [Tue, 3 Jul 2012 07:13:31 +0000 (15:13 +0800)]
After making pclk output ahead of LVDS_SHDN# , data output is later than
panel ready then caused partial black screen. Force triggered data output to
get it fixed.

Bug 972377
Bug 976081
Bug 1001434

Change-Id: Icd455d7439f622e46295158a5435286c521526aa
Signed-off-by: Roger Hsieh <rhsieh@nvidia.com>
Reviewed-on: http://git-master/r/113164
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

drivers/video/tegra/dc/dc.c

index 77cd19e..1f7e2ce 100644 (file)
@@ -1286,15 +1286,19 @@ static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
        if (dc->out_ops && dc->out_ops->enable)
                dc->out_ops->enable(dc);
 
-       if (dc->out->postpoweron)
-               dc->out->postpoweron();
-
        /* force a full blending update */
        dc->blend.z[0] = -1;
 
        tegra_dc_ext_enable(dc->ext);
 
        trace_printk("%s:enable\n", dc->ndev->name);
+
+       tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
+       tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
+
+       if (dc->out->postpoweron)
+               dc->out->postpoweron();
+
        return true;
 }