{ "sclk", "pll_p_out4", 108000000, true },
{ "hclk", "sclk", 108000000, true },
{ "pclk", "hclk", 54000000, true },
+ { "wake.sclk", NULL, 250000000, true },
#endif
{ "sbc1.sclk", NULL, 40000000, false},
{ "sbc2.sclk", NULL, 40000000, false},
{ "pll_c_out1", "pll_c", 208000000, false },
#endif
{ "wake.sclk", NULL, 250000000, true },
- { "sbc5.sclk", NULL, 40000000, false},
- { "sbc6.sclk", NULL, 40000000, false},
{ "sbc1.sclk", NULL, 40000000, false},
{ "sbc2.sclk", NULL, 40000000, false},
{ "sbc3.sclk", NULL, 40000000, false},
{ "sclk", "pll_p_out2", 102000000, true },
{ "pll_p_out4", "pll_p", 204000000, true },
{ "host1x", "pll_p", 102000000, false },
+ { "cl_dvfs_ref", "pll_p", 54000000, false },
+ { "cl_dvfs_soc", "pll_p", 54000000, false },
#else
{ "pll_p_out2", "pll_p", 108000000, false },
{ "sclk", "pll_p_out2", 108000000, true },
{ "pll_p_out4", "pll_p", 216000000, true },
{ "host1x", "pll_p", 108000000, false },
+ { "hclk", "sclk", 108000000, true },
+ { "pclk", "hclk", 54000000, true },
#endif
{ "wake.sclk", NULL, 250000000 true },
{ "cl_dvfs_ref", "pll_p", 54000000, false },