ARM: Tegra: clock: Change default state of pll_p_out3
Prashant Gaikwad [Mon, 15 Oct 2012 13:40:37 +0000 (18:40 +0530)]
pll_p_out3 was kept on since some peripherals had it as
fixed parent. Currently all drivers for those peripherals
implement enable/disable for clocks derived from it.
No need to keep it enabled all the time.

Bug 1155689

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/144572
(cherry picked from commit aa8df6af70b835eff2e150bd1f11e71313f982fa)

Change-Id: I33b3268bcf1abcdf483b4166df993538324f2b26

Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Change-Id: I7ea5d46a219138b14cb540c60dbbdf80d341526b
Reviewed-on: http://git-master/r/146354
Reviewed-by: Automatic_Commit_Validation_User

arch/arm/mach-tegra/common.c

index dd6d737..14cc5b3 100644 (file)
@@ -310,7 +310,7 @@ static __initdata struct tegra_clk_init_table tegra11x_clk_init_table[] = {
        { "sclk",       NULL,           0,              true },
        { "pll_p",      NULL,           0,              true },
        { "pll_p_out1", "pll_p",        0,              false },
-       { "pll_p_out3", "pll_p",        0,              true },
+       { "pll_p_out3", "pll_p",        0,              false },
 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
        { "pll_m_out1", "pll_m",        275000000,      false },
        { "pll_p_out2",  "pll_p",       102000000,      false },