arm: tegra3: change min_rate for sclk
Amit Kamath [Mon, 2 Apr 2012 11:52:57 +0000 (16:52 +0530)]
Change the minimal rate of sclk to 12 MHz and set the lowest
frequency of sbus to be 40 MHz when display is on.

bug 939415

Original change http://git-master/r/#change,76959

Change-Id: I81cda6a95494764721c1be5b4001c476f3aed6ab
Signed-off-by: Amit Kamath <akamath@nvidia.com>
Reviewed-on: http://git-master/r/93850
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arch/arm/mach-tegra/common.c
arch/arm/mach-tegra/pm.c
arch/arm/mach-tegra/tegra3_clocks.c

index 46ddf91..4786ace 100644 (file)
@@ -181,6 +181,7 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
        { "sclk",       "pll_p_out4",   102000000,      true },
        { "hclk",       "sclk",         102000000,      true },
        { "pclk",       "hclk",         51000000,       true },
+       { "wake.sclk",  NULL,   40000000,       true },
        { "sbc5.sclk",  NULL,           40000000,       false},
        { "sbc6.sclk",  NULL,           40000000,       false},
 #endif
index 859694c..40bd28a 100644 (file)
@@ -1293,13 +1293,18 @@ static int tegra_debug_uart_syscore_init(void)
 arch_initcall(tegra_debug_uart_syscore_init);
 
 #ifdef CONFIG_HAS_EARLYSUSPEND
+static struct clk *clk_wake;
 static void pm_early_suspend(struct early_suspend *h)
 {
+       if (clk_wake)
+               clk_disable(clk_wake);
        pm_qos_update_request(&awake_cpu_freq_req, PM_QOS_DEFAULT_VALUE);
 }
 
 static void pm_late_resume(struct early_suspend *h)
 {
+       if (clk_wake)
+               clk_enable(clk_wake);
        pm_qos_update_request(&awake_cpu_freq_req, (s32)AWAKE_CPU_FREQ_MIN);
 }
 
@@ -1310,6 +1315,7 @@ static struct early_suspend pm_early_suspender = {
 
 static int pm_init_wake_behavior(void)
 {
+       clk_wake = tegra_get_clock_by_name("wake.sclk");
        register_early_suspend(&pm_early_suspender);
        return 0;
 }
index 0b2d4f4..0bceeeb 100644 (file)
@@ -3958,7 +3958,7 @@ static struct clk tegra_clk_pclk = {
        .reg_shift      = 0,
        .ops            = &tegra_bus_ops,
        .max_rate       = 167000000,
-       .min_rate       = 40000000,
+       .min_rate       = 12000000,
 };
 
 static struct raw_notifier_head sbus_rate_change_nh;
@@ -4301,6 +4301,7 @@ struct clk tegra_list_clks[] = {
        SHARED_CLK("usb1.sclk", "tegra-ehci.0",         "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("usb2.sclk", "tegra-ehci.1",         "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("usb3.sclk", "tegra-ehci.2",         "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
+       SHARED_CLK("wake.sclk", "wake_sclk",    "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("mon.avp",   "tegra_actmon",         "avp",  &tegra_clk_sbus_cmplx, NULL, 0, 0),
        SHARED_CLK("cap.sclk",  "cap_sclk",             NULL,   &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING),
        SHARED_CLK("floor.sclk", "floor_sclk",          NULL,   &tegra_clk_sbus_cmplx, NULL, 0, 0),